About the Enhancement Request category
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0
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943
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October 6, 2016
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ToVerilogWarning: Output port is read internally:
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6
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495
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April 23, 2022
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Cosimulation with verilator?
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13
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1444
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April 14, 2020
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Allow kwargs in module interfaces
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3
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883
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January 21, 2020
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Simplified signal naming when possible
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6
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1019
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January 20, 2020
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Could modbv support non powers of two?
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10
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1127
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December 23, 2018
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Coalesce identical sequential blocks into the same block?
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9
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966
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December 22, 2018
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Conversion hierarchy extraction?
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8
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810
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December 10, 2018
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VHDL Bit string representation
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15
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1677
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November 5, 2018
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Formal methods and MyHDL
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2
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947
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August 29, 2018
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Add new Bool type to MyHDL?
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9
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868
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July 5, 2018
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Matching a signal against a bitvector
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9
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1328
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July 1, 2018
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Sort signal declarations in generated VHDL
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3
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985
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October 5, 2017
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Add support for nested functions
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4
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1830
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June 21, 2017
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Making cosimulation more user friendly
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2
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1997
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April 26, 2017
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On the design of state-machines
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3
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1225
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April 5, 2017
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Generating hierarchical VHDL
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1
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1054
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March 2, 2017
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Instanciate undefined Signal()
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8
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1666
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October 20, 2016
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Intbv and the .next attribute
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2
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1261
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October 17, 2016
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Conflict: print()
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5
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1380
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June 23, 2016
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