MyHDL Discourse


Bug The category is applied to support questions that could be bugs (and not limitations). Tests should be created for all topics with the Bug category and a pull-request generated. FAQ This category addresses frequently asked questions [FAQ], see also the <a href=""></a> <a href="">FAQ page</a>
About the Support category [Support] (1)
Don't care / unknown [Support] (1)
Function not converting, but deflated code does [Support] (6)
How to simulate for the ROM type design [Support] (18)
'tuple' object has no attribute 'config_sim' [Support] (2)
Changing testbench inputs during a simulation [Support] (9)
Instantiating FPGA components [Support] (8)
Combinational tree like accumulatioin [Support] (7)
Cosimulation myhdl.vpi search path [Support] (3)
VHDL constant value overflow [Bug] (16)
Using standart Python modules [Support] (3)
Verilog width expansion and reduction operator equivalence? [Support] (3)
Invoke Verilog generate for Python list handling [Support] (2)
How to use counters similiar to verilog using for loops? [Support] (11)
Variables in VHDL conversion [Bug] (16)
I don't get how to convert to VHDL [Support] (4)
From myHDL to syntesis [Support] (9)
Is it sensible to yield a delay of zero? [Support] (4)
VHDL conversion - missing constant [Support] (4)
Convert FROM vhdl [Support] (2)
Requirement: 800+ function inputs/outputs (pinmux) [Support] (18)
Explicitly listing instances and instances() give different output (solved) [Bug] (3)
Conversion of list of objects [Support] (2)
Instances are renamed every time in MyHDL 0.10 [Bug] (4)
Instance-specific constants in VHDL conversion [Support] (17)
Porting out a list of 8 bools as an 8-bit vector [Support] (7)
Grabbing a bit from a configuration register [Support] (3)
myhdl.AlwaysCombError: signal used as inout in always_comb function argument [Support] (4)
Inverting a signal passed into a module [Support] (3)
Biquad filter produces garbage (solved) [Support] (7)