MyHDL Discourse

Support


FAQ This category addresses frequently asked questions [FAQ], see also the <a href="http://myhdl.org">myhdl.org</a> <a href="http://www.myhdl.org/support/faq.html">FAQ page</a> Bug The category is applied to support questions that could be bugs (and not limitations). Tests should be created for all topics with the Bug category and a pull-request generated.
Topic Replies Created
About the Support category 1 May 15, 2016
Large memory consumption 12 April 10, 2019
Preserve hierarchy 5 April 15, 2019
Vendor specific instance simulation 2 April 17, 2019
Conversion naming issue 9 April 3, 2019
Verilog conversion to write results to a file? 13 April 2, 2019
Don't care / unknown 5 March 21, 2019
Function not converting, but deflated code does 9 March 12, 2019
How to simulate for the ROM type design 18 March 8, 2019
'tuple' object has no attribute 'config_sim' 2 February 24, 2019
Changing testbench inputs during a simulation 9 February 1, 2019
Instantiating FPGA components 8 January 22, 2019
Combinational tree like accumulatioin 7 December 4, 2018
Cosimulation myhdl.vpi search path 3 February 19, 2018
VHDL constant value overflow
Bug
16 August 29, 2018
Using standart Python modules 3 October 9, 2018
Verilog width expansion and reduction operator equivalence? 3 October 6, 2018
Invoke Verilog generate for Python list handling 2 March 28, 2017
How to use counters similiar to verilog using for loops? 11 September 20, 2018
Variables in VHDL conversion
Bug
16 August 31, 2018
I don't get how to convert to VHDL 4 September 3, 2018
From myHDL to syntesis 9 August 3, 2018
Is it sensible to yield a delay of zero? 4 July 29, 2018
VHDL conversion - missing constant 4 July 29, 2018
Convert FROM vhdl 2 July 19, 2018
Requirement: 800+ function inputs/outputs (pinmux) 18 July 4, 2018
Explicitly listing instances and instances() give different output (solved)
Bug
3 June 4, 2018
Conversion of list of objects 2 June 1, 2018
Instances are renamed every time in MyHDL 0.10
Bug
4 April 16, 2018
Instance-specific constants in VHDL conversion 17 March 29, 2018