MyHDL Discourse

Connecting signals between modules [Support] (3)
Exception raised on reset signal [Support] (7)
A future for the MyHDL community? ( 2 3 4 ) [Meta] (63)
Moving to 0.1dev broke my design [Support] (2)
Iterating over a group of elements [Support] (4)
Multi-bit latch [Support] (5)
Py.test fails on Ubuntu 16.04 [Support] (3)
Verilog generate for always blocks in myhdl [Support] (5)
Conversion producing invalid register names [Support] (10)
[FAQ] Contributing to MyHDL [FAQ] (1)
Issues and PRs are piling up [Support] (5)
Signals in objects vs. function arguments or method calls [Support] (9)
Testbench conversion (solved) [Bug] (12)
VHDL-open equivalent in MyHDL (solved) [Uncategorized] (17)
Saving testbench data to file (solved) [Support] (3)
How to pass part of the signal to module [Support] (3)
REG intialization without 'always_seq' (solved) [Support] (5)
'concat' not working (solved) [Support] (5)
Help: SDR, DSP, FPGAs and Gnuradio [Support] (5)
VHDL conversion bug (resize of signed signal)? [Bug] (5)
Sort signal declarations in generated VHDL [Enhancement Request] (4)
VHDL block equivalent in MyHDL? [Support] (13)
Python comments into generated verilog as comments [Support] (10)
Synthesisable TristateSignal [Uncategorized] (18)
GSoC #6: Round Modes and Their Behavior [Synopsis] (5)
GSoC #-1: Work Product Summary [Synopsis] (1)
GSoC #8: MyHDL Back-end Source Code Analysis (1) [Synopsis] (1)
Using decorators for common hardware structures [Showcase] (1)
Weird register behavior during simulation [Bug] (3)
GSoC #7: Overflow Modes [Synopsis] (1)