I’m more of a MyHDL user than a developer who submits PRs, but I’ve also noticed a downturn in MyHDL. I just did a Google comparison of search hits for MyHDL compared to migen and it was 125K to 600K (not in our favor). This is admittedly a crude measure, but it is still a benchmark.
While checking-in PRs is important for fixing/enhancing the core language, that may not be enough to save MyHDL. The PRs address issues that mainly concern experienced users. For new users, MyHDL is pretty good as it stands. Still, they aren’t taking the bait. If they did and the population of users grew, it might revitalize this project and the core developers might have more motivation to work on it.
Nobody would say migen is more expressive or beautiful than MyHDL, but it does have the misoc project that allows users to quickly build a processor system with the surrounding infrastructure and get it running on an FPGA. MyHDL seems to be missing that sort of marquee project that draws people in. (If I’m wrong, please point me to it as I haven’t found it.) Most of what I can find is some cores by Chris Felton in addition to the PyFDA filter synthesis tools (which don’t generate Verilog or VHDL). I also found an article by Chris from 2012 with a list of links to MyHDL projects, most of which haven’t been updated in years as well as a few 404 pages. And if you look at this forum, there have been <100 posts in 1-1/2 years, and only three of them are in the Projects category.
So while the quiet of the core developers is a concern, the real problem is that we as a community are failing to tell the story of how useful MyHDL is. We aren’t showcasing our designs for potential converts to see the tangible results of using MyHDL. The result is our base of users is not growing and other HDLs have more momentum.
I really find MyHDL useful and I don’t want to see it die. To help prevent that, over the past few months, I’ve been working on some MyHDL add ons:
myhdlpeek allows you to add Peeker objects to MyHDL code to store waveforms for a set of signals. These signals can be displayed as wave traces or tables in a Jupyter notebook.
pygmyhdl is a thin wrapper around MyHDL that attempts to smooth-out some of the rough spots in the syntax. It’s mainly “training wheels” for new users and I expect they’ll abandon it and move on to straight MyHDL once they gain experience.
I’ve got a sequence of Jupyter notebooks that use pygmyhdl, myhdlpeek and yosys/arachne/icestorm to do complete (but elementary) designs for the Lattice iCEstick in MyHDL. A new user can design, simulate, synthesize, place-and-route, and download to the FPGA without leaving the notebook using either Windows or Linux (or even an RPi).
None of these projects, alone or in combination, can save MyHDL. One person can’t do that, not even Chris. But if enough people put enough projects out there, maybe we can build the critical mass that will attract more people to MyHDL. And maybe that will reawaken the core developers or even bring in new ones.
If anyone is willing to showcase their projects, I can build a “MyHDL Projects” page similar to this one I built for KiCad add-on tools. Adding your project would be as simple as modifying the project list page and submitting a pull request as explained here.