MyHDL Discourse

A future for the MyHDL community?


The MyHDL site is just a reflection a markdown pages in github, you do the exact same thing to have it on github /

The directions I linked previous outline the process, you create a pull-request to add new stuff.


We can simply add a link to the site pointing to @devbisme’s repo page, at this point there is enough momentum, I don’t see an issue leaving the list where @devbisme created it.

If the general consensus is to create a page on we can simply move @devbisme’s to site-myhdl/docs/ (I can do this, already have … resource list pull-request ).

I created the pull-request to provide an example how to contribute to the site. As I first stated, I have no issue leaving the resource repo where it is (maybe prefer).


I’ve noticed that many PRs have been reviewed and accepted.
Who can merge them in main branch ?


Only our BDFL @jandecaluwe and @jck can , but we don’t seem to get any reaction. I sent another e-mail and then tweeted a call for help, but to no avail …


That’s really annoying.

Christopher, do you have any information to share ?

How can we go ahead ?


Sorry I have no information.


Great, I’ll look into this tutorial as I get back into MyHDL. When design realization is the immediate goal, cookbook examples are the shortest route for me.

The MyHDL manual seems to have been written by experts and for for experts. I have had great difficulty in using some of the short code snippets due to their lack of context. I doubt that I am alone in my dyslexic confusion of similar and opposite expressions.

MyHDL has been great for me, and I would very much like it to continue.

Jan Coombs


@JanCoombs it will continue, in what form is TBD.


As a beginner, I found this blog and below link very useful.

Also, below is the new-sort url for the myhdl-guide…


MyHDL documentation is a reference documentation.
Reference documentations always lack some practical examples.
I still have in mind to write a tutorial starting from very basic examples to quite complex designs.
But I miss time.
Another point is that I use a modified version of MyHDL and I don’t intend to roll-back for the tutorial.


This the issue I wanted to stress: because of lack of interest from our BDFL we all have diverged MyHDL libraries …


For those who are interested, I have updated my github repo :
The differences with official repo are :

  • Fixes by hgomersall (enhance namespace management)
  • Fix an issue when converting to VHDL (signed casted to unsigned while it should not)
  • Improved simulation configuration (progress callback, optional backup of simulation file, timescale, output directory…)
  • Added an Unsigned() method to intbv (to allow casting a signed to unsigned)
  • Added NotUsed() to remove warnings when converting to VHDL
  • Sort signals, process sensitivity list and other when converting to VHDL (this allows to always generate the same VHDL output when converting a MyHDL source file)
  • Added the possibility to attach attributes to signals. These attributes do nothing in simulation but are converted to VHDL. They allow to define pin location, pin pull-up, pin drive strength, RAM inference style…

These modifications are working with my designs. I don’t guarantee they are free of bugs.


See, that doesn’t work. If we all publish our ‘diverged’ code we are nowhere nearer to a unified and improved MyHDL library. I also have some fixes, with a different approach. @hgomersall has a few more, as does @cfelton, as does …


It is possible, just requires more work from us in the near-term.


Sorry for the delay, but I’ve not been well, and the dog ate my homework.

I have a project which is overdue for release which should attract wide interest and further controversy from users and fixers of floating point arithmetic.

There are two release goals:

  1. A tiny processor in which the sole supported data type is an unconstrained integer. This would interest a small group of programmers, and release would prove the ability to handle variable-sized data items efficiently. Most code is written and slightly tested. A more flexible and simplified test harness is in progress. Expected size: ~3k LUT4s.

  2. A similar processor where the single data type is Unum type 1. This data type is a superset of integer and float, both unconstrained. From planning details the added complexity over release 1) is estimated at 50%. Details of the advantages of Unum type 1 are below [1], but note that my binary number format differs significantly.

Jan Coombs

[1] Unums type 1.

RichReport Gustafson interview 2015-03-01:

Book, etc:



An interesting subject. However it would be better if you started a new thread for this subject. The ShowCase category seem appropriate, I’d say.



Thanks for the suggestion. I’m happy to start a new thread for this divergent topic. Is it possible to move the posting? Or does it need copying and maybe deleting? If anyone can do this easily then please go ahead.

Otherwise I’ll copy and repost tonight, and refine it if possible.

Jan Coombs



I’m just a mere user …
So I guess you have to go through the copy/paste/edit/delete motions.




I agree with you.
My intent is to share the modifications I made to MyHDL.This can be of interest to other users.


Showcase is for work completed, but neither of my release goals have yet been reached, so maybe that category is not suitable, but hopefully will be soon.

Since I would like a sleeping partner, or whipping boy, or something like that, anyone interested could email me directly rather than post here if this helps keep the topic cleaner:

jan4myhdl at murray-microft dot co dot uk

BTW, the 3k LUT4s [+Flops + block RAMs] is system size, so the project really is tiny.

Jan Coombs