Coming from a microcontroller background, it is common to interface to a peripheral (such as a UART) and one can set a register from outside the peripheral, and internally the peripheral can clear it.
I started a new design and sometimes as you do when hacking code quickly I had everything in the same file, everything works great. Then I started trying to clean things up and I wanted to put my UART into it’s own file/module (sorry I don’t know what that is called in myhdl).
But, now the code doesn’t compile, since two separate sequential blocks (again, not sure of the terminology) try to write to the same signal (external to the UART I try to set the transmitting bit, internal I try to clear it).
It might be complex for the myhdl conversion code but it seems possible that IDENTICAL sequential blocks (eg always_seq) with the same clock edge, same reset signal, same other attributes) could be converted into HDL in the same sequential block.
So, as far as code organisation I can have my modules all nicely separated into separate files and I can instantiate them hierarchically, but in terms of the HDL it is as though I was lazy and it was all in the same sequence block.
This could be an option to enable when doing conversion, in case it would have adverse effects on existing code? I don’t see how it would, but I am very inexperienced with HDL etc.