I am having difficulty with Verilog conversion of a concatenation expression:

```
ONE = bool(1)
ZERO = bool(0)
EIGHT_ZEROS = 0b1010101010101010
PREAMBLE_B = 0b10011100
PREAMBLE_M = 0b10010011
PREAMBLE_W = 0b10010110
parity = bdata[0] ^ bdata[1] ^ bdata[2] ^ bdata[3] ^ bdata[4] ^ bdata[5] ^ bdata[6] ^ bdata[7] \
^ bdata[8] ^ bdata[9] ^ bdata[10] ^ bdata[11] ^ bdata[12] ^ bdata[13] ^ bdata[14] ^ bdata[15]
shiftReg.next[64:] = concat(bin(PREAMBLE_W), bin(EIGHT_ZEROS), \
ONE, bdata[0], ONE, bdata[1], ONE, bdata[2], ONE, bdata[3], \
ONE, bdata[4], ONE, bdata[5], ONE, bdata[6], ONE, bdata[7], \
ONE, bdata[8], ONE, bdata[9], ONE, bdata[10], ONE, bdata[11], \
ONE, bdata[12], ONE, bdata[13], ONE, bdata[14], ONE, bdata[15], \
bin(0b10), bin(0b10), bin(0b10), ONE, bin(parity))
```

This is converted as

```
parity = (((((((((((((((bdata[0] ^ bdata[1]) ^ bdata[2]) ^ bdata[3]) ^ bdata[4]) ^ bdata[5]) ^ bdata[6]) ^ bdata[7]) ^ bdata[8]) ^ bdata[9]) ^ bdata[10]) ^ bdata[11]) ^ bdata[12]) ^ bdata[13]) ^ bdata[14]) ^ bdata[15]);
spdif_tx_1_shiftReg[64-1:0] <= {bin(150), bin(43690), 1, bdata[0], 1, bdata[1], 1, bdata[2], 1, bdata[3], 1, bdata[4], 1, bdata[5], 1, bdata[6], 1, bdata[7], 1, bdata[8], 1, bdata[9], 1, bdata[10], 1, bdata[11], 1, bdata[12], 1, bdata[13], 1, bdata[14], 1, bdata[15], bin(2), bin(2), bin(2), 1, bin(parity)};
```

I have minimal Verilog knowledge, but `bin`

does not appear to be a valid operator (Vivado gives a synthesis error). If I strip those away manually and leave the numeric constants “naked”, Vivado says “concatenation with unsized literal; will interpret as 32 bits”—not what we want. Is this a bug in the Verilog conversion, and/or should I be expressing my literals some other way?

BTW it’s a shame literals like “0b101” cannot be used directly in a concat(), since they [obviously] have a defined bit width already, but I imagine this is a limitation from Python?

Thanks.