Conversion from VHDL problems


#1

Hi,

I’m trying to translate existing VHDL code to MyHDL. The original code is from Lattice simulation model for MACHXO2 fifo8kb integrated block.
My goal is to translate the VHDL code in MyHDL for simulation only.

I have hard time on some points :
Part of the VHDL code is :

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.vital_timing.all;
    use ieee.vital_primitives.all;
    use ieee.std_logic_unsigned.all;
    use work.global.gsrnet;
    use work.global.purnet;
    use work.mem3.all;
    
    -- entity declaration --
    ENTITY fifo8kb IS
       GENERIC (
            DATA_WIDTH_W               : Integer  := 18;
            DATA_WIDTH_R               : Integer  := 18;
            REGMODE                    : String  := "NOREG";
            RESETMODE                  : String  := "ASYNC";
            ASYNC_RESET_RELEASE        : String  := "SYNC";
            CSDECODE_W                 : string  := "0b00";
            CSDECODE_R                 : string  := "0b00";
            AEPOINTER                  : String  := "0b00000000000000";
            AEPOINTER1                 : String  := "0b00000000000000";
            AFPOINTER                  : String  := "0b00000000000000";
            AFPOINTER1                 : String  := "0b00000000000000";
            FULLPOINTER                : String  := "0b00000000000000";
            FULLPOINTER1               : String  := "0b00000000000000";
            GSR                        : String  := "DISABLED";
                );
       PORT(
            di0, di1, di2, di3, di4, di5, di6, di7, di8            : in std_logic := 'X';
            di9, di10, di11, di12, di13, di14, di15, di16, di17    : in std_logic := 'X';
            fulli, csw0, csw1, emptyi, csr0, csr1                  : in std_logic := 'X';
            we, re, clkw, clkr, rst, rprst, ore          : in std_logic := 'X';
    
            do0, do1, do2, do3, do4, do5, do6, do7, do8            : out std_logic := 'X';
            do9, do10, do11, do12, do13, do14, do15, do16, do17    : out std_logic := 'X';
            ef, aef, aff, ff                                       : out std_logic := 'X'
            );
            
    END fifo8kb ;
    
    -- ARCHITECTURE body --
    ARCHITECTURE V OF fifo8kb IS

        SIGNAL wclk_ipd  : std_logic := '0';
    
        SIGNAL rst_ipd1   : std_logic := '0';
        SIGNAL rst_ipd2   : std_logic := '0';
                    
        SIGNAL g_reset   : std_logic := '0';
        SIGNAL pur_reset   : std_logic := '0';
        
    BEGIN

       GLOBALRESET : PROCESS (purnet, gsrnet)
        BEGIN
          IF (GSR =  "DISABLED") THEN
             g_reset <= purnet;
          ELSE
             g_reset <= purnet AND gsrnet;
          END IF;
    
          pur_reset <= purnet;
        END PROCESS;


      S11 : PROCESS(adw_node_syncb, rprst_ipd, addr_valid, rst_ipd)
      VARIABLE  adw_var_syncb : std_logic_vector(ADDR_WIDTH_W downto 0);
      BEGIN
         adw_var_syncb := adw_node_syncb + '1';
    
         IF (rst_ipd = '1') THEN
            adwf_node_syncb <= (others => '0');
         ELSIF (rprst_ipd = '1') THEN
            adwf_node_syncb <= (adw_var_syncb_rst(ADDR_WIDTH_W downto 0) & ((12 - ADDR_WIDTH_W) downto 0 => '0'));
         ELSIF (addr_valid'event) THEN 
            adwf_node_syncb <= (adw_var_syncb(ADDR_WIDTH_W downto 0) & ((12 - ADDR_WIDTH_W) downto 0 => '0'));
         END IF;
      END PROCESS;
    
    END V;

Please note that gsrnet and purnet are chip global signals that are not passed to the entity.

I have translated this code

       GLOBALRESET : PROCESS (purnet, gsrnet)
        BEGIN
          IF (GSR =  "DISABLED") THEN
             g_reset <= purnet;
          ELSE
             g_reset <= purnet AND gsrnet;
          END IF;
    
          pur_reset <= purnet;
        END PROCESS;

to this code

    gsrnet = Signal(bool(0))
    purnet = Signal(bool(0))

    g_reset = Signal(bool(0))
        pur_reset = Signal(bool(0))

        # GLOBALRESET 
        @always(purnet, gsrnet)
        def proc_glb_rst():
            if self.GSR == "DISABLED" :
                g_reset.next = purnet
            else :
                g_reset.net = purnet and gsrnet
         
            pur_reset.next = purnet

When running simulation I get an exception on the decorator line :
AttributeError: ‘bool’ object has no attribute 'net’
I wasn’t able to fix it.

Also, how do I translate this part of code ?

      S11 : PROCESS(adw_node_syncb, rprst_ipd, addr_valid, rst_ipd)
      VARIABLE  adw_var_syncb : std_logic_vector(ADDR_WIDTH_W downto 0);
      BEGIN
         adw_var_syncb := adw_node_syncb + '1';
    
         IF (rst_ipd = '1') THEN
            adwf_node_syncb <= (others => '0');
         ELSIF (rprst_ipd = '1') THEN
            adwf_node_syncb <= (adw_var_syncb_rst(ADDR_WIDTH_W downto 0) & ((12 - ADDR_WIDTH_W) downto 0 => '0'));
         ELSIF (addr_valid'event) THEN 
            adwf_node_syncb <= (adw_var_syncb(ADDR_WIDTH_W downto 0) & ((12 - ADDR_WIDTH_W) downto 0 => '0'));
         END IF;
      END PROCESS;

The addr_valid’event statement is both posedge and negedge. How to translate this in MyHdl ?


#2

First problem fixed. The issue was a typo here :

g_reset.net should be written g_reset.next of course.
I 've been abused by the location of the exception (the decorator line).

Working on the issue…


#3

I’ve created a small design to work on my second issue.
It looks like that to create a process acting on both edges of a clk, one can use :
@always(i_clk.posedge, i_clk.negedge)
or simply
@always(i_clk)

It seem both are the same. Right ?


#4

Does addr_valid'event synthesizable in your case?


#5

Yes, it is synthesizable.