MyHDL Discourse

Conversion hierarchy extraction?


#1

Does someone work on hierarchy extraction in VHDL/verilog converter ?


#2

It’s something I’ve been thinking about, but don’t yet have anything. Perhaps others do? There are some subtleties that need to be addressed in how to design the interfaces…


#3

Can you elaborate on this ?

Looking at _ToVHDL.py, I noticed global variables are used. This is will be a problem.


#4

Right - I think there needs to be fully elaborated block level implementation before we can have a hierarchy. The netlists are currently implicit through global signals, but the connections will need to be made explicit between each level in the hierarchy.


#5

Is there a document describing how the elaboration works ?
Understanding the code is quite hard.


#6

Nope and yep. There has been much discussion about this over on gitter.


#7

Is there a document describing how the elaboration works ?
Understanding the code is quite hard.

The VHDL converter would definitely benefit from adding, e.g., doc strings to each function. Can I perhaps persuade everyone who knows their way around the code to add some helpful comments whenever they touch the code? It would make it easier for new contributors to get started.


#8

@hgomersall What do you think would be the best way to go ahead ?


#9

@DrPi I think head over to gitter and join the conversation!