Error in the converted verilog code

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@Ravi_Jain
I was wrong, it doesn’t work in VHDL either.

outp <= (to_unsigned(0, 21) & rdindex & wrindex)(31 downto 0);

ModelSim complains:

** Error: C:\Users\Josy\workspace-CC-Logic\Experiments\rj\myblock.vhd(58): near "(": (vcom-1576) expecting ';'.

And for this Verilog code:

        outp <= {21'h0, rdindex, wrindex}[32-1:0];

ModelSIm claims:

** Error: C:\Users\Josy\workspace-CC-Logic\Experiments\rj\myblock.v(35): Illegal part-select expression

Looks like your workaround, using an intermediate signal, is the best option. I can think of a way to do this in VHDL, but don’t know Verilog well enough to even have an idea.