GSoC #4: Point Alignment of Fixed-Point Type


Origin blog post is here.

This time it leaves a question…

In the previous post, I thought the point alignment of fixbv should be implemented in a short time. Soon I found myself wrong.

After fixing a compatibility bug in the unit test, the problem of point alignment has been revealed.

If point alignment only solved in, in the case of a variable of Signal plus or minus a variable of fixbv, MyHDL simulator will throw a problem. So I have to implement both in Signal.__add__ and fixbv.__add__. Also, I have to consider if they plus or minus intbv.

So, it causes a problem of cross import. I posted this StackOverflow question and you may see the implementation.

Temporarily, my solution is (in fixbv.__add__):

    def __add__(self, other):
        if isinstance(other, fixbv):
            iW = self._W + other._W
            # Solve the case if `type(other) is Signal`
            return other.__radd__(self)

This implementation only considered fixbv and Signal. However, if I consider intbv, things might be more complex.

It leaves a question I am going to solve now.