GSoC fixbv #2: Configuration of Cosimulation


#1

Original post: http://qren.logdown.com/posts/2017/06/01/1905464


To make full use of MyHDL, it is strongly recommended to install and configure cosimulation modules. So that the output (Verilog/VHDL code) of MyHDL compiler backend can be evaluated, and the current MyHDL code can work with the conventional code base and migrate into industrial EDA workflow.

Here, I assume that MyHDL has been installed by the steps in the previous post.

Installing Icarus Verilog

MyHDL supports several popular RTL simulators. At this time, Icarus Verilog, GHDL, cver, and ModelSim were supported. Here, Icarus Verilog will be used as an example.

Icarus Verilog is already in some Linux distributions. For example, in Ubuntu, type the following command to install Icarus Verilog:

sudo apt install iverilog

For Windows users, Windows binaries might be useful.

VPI module

VPI module provides an interface for Verilog to share data with MyHDL.

Compiling VPI module

In the source code of MyHDL, the cosimulation folder contains several types of simulator that supported. In each subfolder, the README file describes how to install MyHDL support for these simulators.

For Icarus Verilog, go to cosimulation/icarus, and then use command make to compile the vpi module. Then, you will get myhdl.vpi after compiling.

You can copy myhdl.vpi to other places while needed.

Check installation

cd myhdl/test/core
py.test test_Cosimulation.py

Follow cosimulation chapter of the manual could also make sense, especially when you want to get a direct message of why the cosimulation does not work.

Please refer to corresponding manpages to get the meanings of options for iverilog and vvp.