Help needed: myHDL as a part of the pyFDA project

All,

I’ve been developing the open source filter design tool pyFDA (Python Filter Design and Analysis, any naming similarity with commercial tools is purely coincidental :wink: ) with a GUI in python for quite a while now. You can check it out under https://github.com/chipmuenk/pyfda if you like, it runs under Python 2 an 3 and pyQt4 and 5.

My goal right from the start was to use myHDL for simulating the designed filters with fixpoint / integer arithmetics and generating VHDL / Verilog code. Target users are hobbyists and professionals designing highlevel code, uCs and FPGAs for digital signal processing. The “unique selling point” should be analysis, design and synthesis of IIR and other hardware-efficient filters. The current status of pyFDA is: When myHDL is installed, an extra tab shows up (it’s a kind of easter egg right now) allowing fixpoint simulation for IIR filters (works, but only for second order filters and only in the root directory) and Verilog export (crashes the program with the message " ‘Call’ object has no attribute ‘starargs’ ").

Chris Felton gave me some valuable hints, but I’m pretty much stranded now: I’m trying to pass filter coefficients in either polynomial or SOS form and filename / path from pyFDA to the siir.py routine written by Chris a few years ago. I’ve designed logic and fixpoint DSP with VHDL and (obviously) I’ve done some Python programming but I find it hard to get started with myHDL. It would be great to have someone with myHDL experience to give me an entry point, explaining how to interface to myHDL and get the code running.

As a long term goal I’d like to be able to select between different filter topologies like direct form, SOS, LDI, … but hopefully I’ll manage to implement the VHDL description in Python/myhdl myself (although help / cooperation would be very welcome :grin: ).

A happy and healthy 2017 to all of you and to myHDL!

Christian

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Christian,

All the best in 2017, especially lots of fun with MyHDL :joy:

I don’t know much about filters … But your project looks interesting, so I decided to check it out and learn something.
I installed pyFDA (Python 2.7.9 win32), struggled with scipy and eventually downloaded a wheel or two from Christoph Gohlke’s Unofficial Windows Binaries for Python Extension Packages.
I tried generating a V* output file for a 10 stage low-pass IIR Bessel filter, and although the log/terminal window says pyFDA did all the right things, I’m not able to find it.

[   INFO] [pyfda.hdl_generation.hdl_specs:390] Creating hdl_file "D:/Daten/ttt.vhd"
[   INFO] [pyfda.hdl_generation.hdl_specs:393] Using hdl_filename "ttt"
[   INFO] [pyfda.hdl_generation.hdl_specs:394] Using hdl_dirname "D:/Daten/ttt"
init_SIIR
('b', array([ 0.00035876,  0.0035876 ,  0.01614419]))
(<type 'numpy.ndarray'>, array([ 0.00035876,  0.0035876 ,  0.01614419]))
('a', array([ 1.        , -1.77859231,  2.25022238]))
('fxa', 3, array([ 1.        , -1.77859497,  2.25021362]))
('fxb', 3, array([ 0.00036621,  0.00360107,  0.0161438 ]))
('IIR w,b,a', 0, array([ 0.00035876,  0.0035876 ,  0.01614419]), array([ 1.        , -1.77859231,  2.25022238]))
('IIR fixed-point b,a', (12, 118, 529), (32768, -58281, 73735))
Convert IIR to Verilog and VHDL
[   INFO] [pyfda.hdl_generation.hdl_specs:401] HDL conversion finished!

It looks like the local MyHDL library is not found (but no message is generated?).

Regards,

Josy

Hello Christian,

I started reworking the HDL filter implementations: https://github.com/cfelton/pyFDA/tree/myhdl_filters/pyfda/hdl_generation

But that was over a year ago :frowning:

For now, lets focus on the “crash” issue, I wasn’t able to reproduce a “crash” with the latest from the github master? I am using the latest myhdl, from the github master stable branch.

@josyb,

It looks like the files should be siir_hdl.v[hd] in which ever directory you ran the pyfdax in. The filename/path are not being used.

@cfelton
yes they are, I had Win10 search for it too, but that always takes too long, and I forgot about it.
Funny, I added a message in toVHDL() and didn’t see that in the output either, so I (wrongly) concluded there was something else not working.

Thanx a lot for trying and thanx to @cfelton for replying faster than I. The problem that I don’t know how to make myHDL use path and filename is one of the things I hope to solve with the people in this forum!

Chris,
I’ll take a look into your updated code tomorrow.

I just did a pip install myhdl which gave me version 0.9.0. Is this really the latest version? At least, it is the latest tag.

I’ve run the code with both python 2.7.12 and python 3.5.2 (Anaconda distribution, Win7, 64 bit). I’ll try once more on my other PC in a Linux environment tomorrow.

The last lines of my crash message are:

File “D:\Programme\Anaconda3\lib\ast.py”, line 245, in visit
return visitor(node)
File “D:\Programme\Anaconda3\lib\site-packages\myhdl\conversion_analyze.py”,
line 264, in visit_Call
if node.starargs:
AttributeError: ‘Call’ object has no attribute ‘starargs’

Thanx once more for looking into the stuff!

@chipmuenk
You can specify the name and the directory:

toVHDL.name = 'tryout'
toVHDL.directory = 'D:/Daten'
toVHDL(designforconversion, arg1, ..., argn)

(the same goes for toVerilog)
Of course the name and the directory have to ripple down to the target code, in this case the SIIR class in filter_iir.py
The other option is to move-rename the generated file to the target directory/name.

@chipmuenk 0.9 is the latest released version (should be 0.9.1, I think will need to look into updating pip). The development branch, master on github, is 1.0dev it is the latest stable but not officially released yet (and there is still some discussion if it should be 0.10).

A decision will need to be made if you want to use the latest and greatest stable branch or the official releases. Note, the myhdl releases are infrequent.

@cfelton As it will take some time until myhdl is really integrated into pyFDA and suitable for “normal” users, I guess it makes more sense to use the latest master release for the moment. myHDL will be a kind of easter egg until then :grin:

If I read between the lines correctly :smirk: both you and @josyb are using the latest and greatest which doesn’t give you the error I’m seeing during HDL export?

I’ll update the myHDL version later today and try again.

I hadn’t noticed your fork of pyFDA - as there are a LOT of commits between the forks I’m currently merging the files manually.

Thanx for the information, I’ll search for the actual conversion call in Chris’ code.

Is it possible to freely select a name for the generated HDL file or does it have to match with the class name? This wouldn’t be a big problem as long as I can select the output directory.

Moving the file after generation would be an option but I’m not sure every user has write permissions in the start directory of pyfdax.

@chipmuenk, yes my fork is old (over a year) and I haven’t reviewed or remember what I did or how far I got. Since the HDL generation is small, manually merging the files probably make the most sense. I might be able to create an updated fork.

That sounds reasonable moving to 1.0 (0.10) there are some API changes that need to be updated, I can make these changes are create a PR.

@cfelton: Thanx for your support! Perhaps it is easier for you to start from the merged state? I’m just in the process of updating / merging your and my changes.

Under which myhdl version are you running the pyfda/myhdl conversion at the moment?

@chipmuenk
Any (valid) name will do, as you actually are overriding the default func.__name__

I had some difficulties installing the latest release of myhdl I’ve downloaded from https://github.com/myhdl/myhdl:

After running python setup.py develop (or install) from the myhdl directory, I had a really old version of pyfda in my path. When re-installing pyfda via python setup.py develop from the pyfda directory, myhdl was no longer found … Probably a noob mistake, I finally succeeded by doing a pip install directly from the zipped myhdl file.

With the new version of myhdl, I can both simulate and generate HDL - files, I only get some depracation warnings.Next step will be to adapt @cfeltons updated (but not yet finished) files, currently, some ends don’t quite meet yet. If somebody would like to experiment with Chris’ version, you just need to uncomment the import statement for hdl_specs in input_tab_widgets.py.

@chipmuenk to test you need to use virtualenv or the conda environments. If you setup a requirements.txt you can automatically install with pip (that is install pyfda and it dependencies). This is the best route to test the latest code from the repo and its dependencies. It can be a pain though - working with virtualenv. Here is an example of requirements.txt, more examples can be found on the web.

@cfelton I’m using conda but I had no idea how to install software without a conda channel or a pypi version number. Thanx for the hint using requirements.txt, it worked somehow within a conda environment but it is somewhat of a pain …

Anyway, thanx to your help and suggestions I am able to pass file- and directory name to the myHDL machinery but now I’m a little lost once more: I can create HDL files for the restricted use case of a biquad IIR, but fix-point simulation terminates due to a fix-point overflow error which I don’t understand as all coefficients are definitely less than one.

@cfelton: Could you take a look at the code? I don’t know which parts are supposed to work and which parts only contain boilerplate code. Would you like to chat about possible further developments? And if so: is this forum a good place or should me move to gitter @pyfda?

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