All,
I’ve been developing the open source filter design tool pyFDA (Python Filter Design and Analysis, any naming similarity with commercial tools is purely coincidental ) with a GUI in python for quite a while now. You can check it out under https://github.com/chipmuenk/pyfda if you like, it runs under Python 2 an 3 and pyQt4 and 5.
My goal right from the start was to use myHDL for simulating the designed filters with fixpoint / integer arithmetics and generating VHDL / Verilog code. Target users are hobbyists and professionals designing highlevel code, uCs and FPGAs for digital signal processing. The “unique selling point” should be analysis, design and synthesis of IIR and other hardware-efficient filters. The current status of pyFDA is: When myHDL is installed, an extra tab shows up (it’s a kind of easter egg right now) allowing fixpoint simulation for IIR filters (works, but only for second order filters and only in the root directory) and Verilog export (crashes the program with the message " ‘Call’ object has no attribute ‘starargs’ ").
Chris Felton gave me some valuable hints, but I’m pretty much stranded now: I’m trying to pass filter coefficients in either polynomial or SOS form and filename / path from pyFDA to the siir.py routine written by Chris a few years ago. I’ve designed logic and fixpoint DSP with VHDL and (obviously) I’ve done some Python programming but I find it hard to get started with myHDL. It would be great to have someone with myHDL experience to give me an entry point, explaining how to interface to myHDL and get the code running.
As a long term goal I’d like to be able to select between different filter topologies like direct form, SOS, LDI, … but hopefully I’ll manage to implement the VHDL description in Python/myhdl myself (although help / cooperation would be very welcome ).
A happy and healthy 2017 to all of you and to myHDL!
Christian