I don't get how to convert to VHDL


I was thinking, there should be a program called myhdl working like:

$ myhdl vhdl hello1.py
…converted to VHDL: hello1.vhd

I know the link:

I read the full page and still don’t know how to convert MyHDL-Code to VHDL. I’m using example code from the tutorial, which outputs:

$ python3 hello1.py
10 Hello World!
30 Hello World!
50 Hello World!
<class ‘myhdl._SuspendSimulation’>: Simulated 50 timesteps

But what am I seeing there? What does this output mean?
How to convert MyHDL-Python-Code to VHDL, seriously?

Actually, I’m new to Python, too. Do I overlook something? I’m using Cygwin shell on Windows.


I guess your hello1.py is something close to this:

from myhdl import block, delay, instance, now

def HelloWorld():

    def say_hello():
        while True:
            yield delay(10)
            print("%s Hello World!" % now())
            yield delay(10)

    return say_hello

inst = HelloWorld()

The last line simulates the design for 50 steps. If you want to convert to VHDL after the simulation, you would add the following line:


Bear in mind, though, that not all code is convertible, and all convertible code is not synthesizable.


OK, that’s working. But

10 Hello World!
30 Hello World!
50 Hello World!

tells me nothing. Is there a way to plot this simulation with ModelSim or another tool?


ModelSim will not tell you anything more, since that’s all the code does. If you add some logic, you can simulate the converted VHDL (or Verilog) in ModelSim. You can also use GTKWave or another VCD viewer to view the signals. Just add the following line before the run_sim() call:

inst.config_sim(backend='myhdl', trace=True)

(But there are no signals in this case. You need to add some logic first.)