Invoke Verilog generate for Python list handling


#1

Hello everyone,

in the last week I tried to get firm with MyHDL. In general I like it very much.
My plan is to use it for a medium size project in an ASIC design flow. Therefore I would like to use Python-lists because excessive routing is necessary.

Because of Verilog is not able to pass arrays (“memory”,e.g.: reg [Nbit:0] arr[0:Ndepth] ) through ports I wrote a class for MyHDL which packs/unpacks intbv/modbv-Bitvectors into Python-lists.
So far so good, MyHDL-Simulation works fine and Verilog can be generated. Now the problem:
The generated Verilog syntax does not fit the convention and cannot be simulated (Icarus Verilog). Working with Verilog lists requires the “generate” and “genvar” keywords for the for loops.
In a special case I got:

// Map Python list to flat output
always @(core_data_o[0], core_data_o[1], core_data_o[2], core_data_o[3]) begin: PACKERTEST_TOP_GHDL_PK_DATA_O_CORE
    integer i;
    for (i=0; i<4; i=i+1) begin
        data_o[((i + 1) * 8)-1:(i * 8)] = core_data_o[i];
    end
end

// Map flat input to Python list
always @(data_i) begin: PACKERTEST_TOP_GHDL_UPK_DATA_I
    integer i;
    for (i=0; i<4; i=i+1) begin
        core_data_i[i] = data_i[((i + 1) * 8)-1:(i * 8)];
    end
end

But I want (which simulates fine):

// Map Python list to flat output
genvar i;
generate
for (i=0; i<4; i=i+1) begin
    always @(core_data_o[0], core_data_o[1], core_data_o[2], core_data_o[3]) begin: PACKERTEST_TOP_GHDL_PK_DATA_O_CORE
        data_o[((i + 1) * 8)-1:(i * 8)] = core_data_o[i];
    end
end

// Map flat input to Python list
generate
for (i=0; i<4; i=i+1) begin
    always @(data_i) begin: PACKERTEST_TOP_GHDL_UPK_DATA_I
        core_data_i[i] = data_i[((i + 1) * 8)-1:(i * 8)];
    end
end
endgenerate

The MyHDL core generating this Verilog is here:

@always_comb
    def core():
        """
        Map Python list to flat output
        """
        for i in range(itemCount):
            parallel_o.next[(i+1)*widthItem: i*widthItem] = list_i[i]

and here:

@always_comb
def core():
""“
Map flat input to Python list
”""
for i in range( itemCount ):
# Listenelement aus Bus holen
list_io[i].next = parallel_i[(i+1)widthItem: iwidthItem]

Is a fast fix possible which may be realized by another keyword like “always_generate” instead of “always_comb” and creates the Verilog generate loop?
It would be very clean if the sensitivity list would contain core_data_o[i] if possible.

Thanks alot :slight_smile: !

Best regards
Flo