Hello are there some free/open source tools with which I could get a rough estimate of resource usage from my myhdl code ? Alternately are there any opensource tools to estimate it from my converted design to Verilog/VHDL ?
Thank you
Hi,
To my knowledge, there is no such tool for MyHDL.
For HVDL/Verilog, all vendor tools give a rough estimation of used resources after synthesis.
Open-source toolchain, expects Verilog source, largest target is ~8k LUT4s, or ~5k with MAC blocks. Usage and timing reports as usual.
http://www.clifford.at/icestorm/
Open source Xilinx 7 toolchain coming soon:
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