Python comments into generated verilog as comments


#1

Is there a way to get comments from MyHDL code output as comments in the generated Verilog code?
We need a way to add lint waivers as comments in the Verilog code and since the Verilog is generated from MyHDL the comments needs to come from the MyHDL source.

If there is no way to do this currently, I would be grateful for any hints on how we could add this to MyHDL.

Kenny


#2

Hi Kenny,

The conversion to V* relies on Python’s AST module which discards comments.
What do these lint waivers look like (both in the MyHDL and the Verilog code)?

Regards,

Josy


#3

The lint waivers in the Verilog code should be done by appending “//
cn_lint_off_line CN_” to each waived line.
How this should be done in MyHDL is not obvious. One simple idea would be
to take end-of-line comments from the Python code and turn them into
corresponding comment in the Verilog.

MyHDL:
a.next = b + c # cn_lint_off_line CN_
translated to Verilog:
a <= b + c // cn_lint_off_line CN_

But if the comments are discarded/unavailable in AST then that may not be
possible. Is the source file and line number available in the AST? Then
maybe it’s possible to get the comment from the original source when doing
the verilog conversion.

 Kenny

#4

Kenny,

I don’t do Verilog, but I wonder why you would need the lint waiver(s)? Or perhaps the example you gave is too simple?

IMHO MyHDL should generate lint-free code…?

There is Baron and RedBaron, which generate a Full Syntax Tree, this is with all source text included, but its deployment in MyHDL will take a while. Not sure if anybody is working/studying this, perhaps @hgomersall?

Regards,

Josy


#5

It’s one of those “When I have some time” projects. I think there is huge scope for using an FST but it obviously needs some work!


#6

You can get comments in the converted code by using doc strings. Personally I don’t think it would be worth it to convert the comments in the myhdl.generators to the converted code since the doc strings exist (just my opinion).

import myhdl
from myhdl import Signal, ResetSignal, intbv, always_seq, always_comb

@myhdl.block
def my_awesome_amazing_block_of_logic(clock, reset, x, y):
    """
    This block of logic is so fantastic it will blow you mind,
    you have never seen anything like it.  It is absolutely 
    amazing ....
    """
    b = Signal(y.val)
    
    @always_seq(clock.posedge, reset=reset)
    def beh_atch():
        """More amazing sequential logic"""
        y.next = b - 1
        
    @always_comb
    def beh_itching():
        """Look at how it is combinatorial"""
        b.next = x + 1
        
    return myhdl.instances()

clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=False)
x = Signal(intbv(0, min=-16, max=16))
y = Signal(intbv(0, min=-17, max=17))
inst = my_awesome_amazing_block_of_logic(clock, reset, x, y)
inst.convert()
%less my_awesome_amazing_block_of_logic.v
// File: my_awesome_amazing_block_of_logic.v
// Generated by MyHDL 1.0dev
// Date: Fri Sep  8 17:35:42 2017


`timescale 1ns/10ps

module my_awesome_amazing_block_of_logic (
    clock,
    reset,
    x,
    y
);
// This block of logic is so fantastic it will blow you mind,
// you have never seen anything like it.  It is absolutely 
// amazing ....

input clock;
input reset;
input signed [4:0] x;
output signed [5:0] y;
reg signed [5:0] y;

wire signed [5:0] b;


// Look at how it is combinatorial

assign b = (x + 1);

// More amazing sequential logic
always @(posedge clock) begin: MY_AWESOME_AMAZING_BLOCK_OF_LOGIC_BEH_ATCH
    if (reset == 0) begin
        y <= 0;
    end
    else begin
        y <= (b - 1);
    end
end

endmodule

#7

Thanks, doc strings was a good idea. That could be a way forward. The only
problem with doc strings is that they are not put on the same line as the
code, as per my example. But I think I can create a script that
post-processes the comments and moves them to the end of the correct line.
Since the layout of the generated Verilog is very regular I think it might
work.

Kenny

#8

@kranerup correct it doesn’t help with your example, I hadn’t read the complete thread just the OP. I agree with @josyb you shouldn’t need to disable the linter, is there a specific example (lint error/warning) you are trying to avoid? Is the linter too strict? Which lint tool are you using?


#9

We can’t avoid triggering the lint rules. We deliver the verilog to customers that then run with their own set of rules. As often is the case with linters the rules are triggered and we analyze the code only to find that there is not a real problem. Thus we need to waive it or rewrite the code just for the sake of the linter.

We will go with the solution to use doc strings that are then post processed to become end of line comments. It would’ve been nice to be able to waive it on the same line in MyHDL but it seems not possible.


#10

Can you show us a (large enough) piece of actual MyHDL code to give us a feeling where you want to waive the linters?
Is there a possibility to waive the complete file?