MyHDL Discourse

Verilog conversion to write results to a file?

#1

Dear All,
Is there an easy way to insert a macro inside the myhdl code to generate a verilog conversion to generate data logs to a file.
Like:
Myhdl Verilog
f = open(“log.txt”,“w+”) $fopen(“log.txt”,“w”);
f.write(…) $fwrite(…);
f.close() $fclose(‘log.txt’);
Thanks
Dan

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#2

Hi,
What kind of information would you like to log ?
Nicolas

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#3

Hi Nicolas,

Like a read/write data sequence in case of not expected returned data.

Rgds,

Dan

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#4

In your first message, you talk about conversion but in your last message its seems you talk about simulation.
Can you clarify ?

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#5

OK let say I don’t need to generate synthesisable verilog for the part that is doing the logging. A want to create a test-bench verilog which logs results. I this more clear ?

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#7

May be but this is a long shot. May be using the ‘verilog_code’ feature can be a quick fix, but so far I didn’t succeed to figure it out. Did someone face the same need ?

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#9

If I understand you correctly : From MyHDL, you want to generate a verilog testbench. This verilog test bench, which is simulated with verilog tools, generates log files containing simulation data.
Is this correct ?

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#10

Dear DrPi,

Yes correct. So if somebody has an example on how to use ‘verilog_code’ to insert the instruction I need I would take if. If not I will add some marker and do it in post processing.

I am surprised that nobody need this kind of feature.

Rgds, Dan

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#11

The standard way is to simulate with MyHDL (you can easily generate log files). When you’re done with your design, you use co-simulation to check the converted design matches the MyHDL design.
But maybe I’m wrong on your needs.

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#12

What means standard way ? I guess lots of people here are doing FPGA. We have are doing something with mixed signals in this case you need a way to simulate low level registers access and … .

This is just to answer your curiosity ( take care it killed the cat :slight_smile: ).

Seems nobody has a simple proposal even with ‘verilog_code’ :(.

Rgds, Dan

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#13

This is not just a matter of curiosity.
There are two options when someone has a request :

  • Stupidly answer the question
  • Understand the need to give a smart answer.

The purpose of my questions is to understand the need.

My stupid answer is : No, it’s not possible.

My smart answer is :
MyHDL is very good at simulation since you can push the limits very far.
You need mixed signal simulation. Why not try with MyHDL ?

You could call ngspice library API from MyHDL for the analogue part. PySpice does this perfectly.
This is just an idea. I have not tested it.

Regards,
Nicolas

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#14

Dear Nicolas,

The mixed signal flow is running ( what you suggest works we tried it several years ago :slight_smile: ).

This is not what we do and we do use myhdl which is very handy to generate the test-bench verilog, it does a fine job in doing all the heavy lifting for us. The only touch we would need is to have the test-bench verilog write to a file.

Any way will do it in post-processing ( open, write, close file ).

Thanks for your support.

Rgds, Dan

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#15

That’s good news :slight_smile:
Don’t hesitate to share your workflow with other MyHDL users :wink:

Regards,
Nicolas

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