# Enhancement Request

**URL:** https://discourse.myhdl.org/c/enhancement-request/10.md

[Latest](https://discourse.myhdl.org/latest.md) · [Categories](https://discourse.myhdl.org/categories.md)

---

## [About the Enhancement Request category](https://discourse.myhdl.org/t/about-the-enhancement-request-category/124)

<div class="topic-metadata">

**Author:** [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Replies:** 0

</div>

---

## [ToVerilogWarning: Output port is read internally:](https://discourse.myhdl.org/t/toverilogwarning-output-port-is-read-internally/534)

<div class="topic-metadata">

**Author:** [@steveg](https://discourse.myhdl.org/u/steveg)\
**Replies:** 6\
**Last updated:** [April 23, 2022, 5:41am UTC](https://discourse.myhdl.org/t/toverilogwarning-output-port-is-read-internally/534 "2022-04-23T05:41:53Z")

</div>

Hi, I find I get benign warning for using my output of my block internally - this looks like a redundant message and should be removed? Its always nice to compile and not get any warnings / errors. Regards, Steve.

---

## [Cosimulation with verilator?](https://discourse.myhdl.org/t/cosimulation-with-verilator/417)

<div class="topic-metadata">

**Author:** [@jos.huisken](https://discourse.myhdl.org/u/jos.huisken)\
**Replies:** 13\
**Last updated:** [April 14, 2020, 7:52am UTC](https://discourse.myhdl.org/t/cosimulation-with-verilator/417 "2020-04-14T07:52:07Z")

</div>

Hi all, I would like to perform cosimulation with verilator, due to its systemverilog language support. Some 10 years ago, mentioned in the sourceforge myhdl-list, an experiment was done by Terry Chen. Not sure if anyo…

---

## [Allow kwargs in module interfaces](https://discourse.myhdl.org/t/allow-kwargs-in-module-interfaces/404)

<div class="topic-metadata">

**Author:** [@jvillar](https://discourse.myhdl.org/u/jvillar)\
**Replies:** 3\
**Last updated:** [January 21, 2020, 1:22pm UTC](https://discourse.myhdl.org/t/allow-kwargs-in-module-interfaces/404 "2020-01-21T13:22:52Z")

</div>

Hi! There are use cases where not all members of an interface are known at coding time, let’s think about a highly parameterizable component that can modify it’s interface depending on the value of certain parameters, s…

---

## [Simplified signal naming when possible](https://discourse.myhdl.org/t/simplified-signal-naming-when-possible/403)

<div class="topic-metadata">

**Author:** [@jvillar](https://discourse.myhdl.org/u/jvillar)\
**Replies:** 6\
**Last updated:** [January 20, 2020, 6:19pm UTC](https://discourse.myhdl.org/t/simplified-signal-naming-when-possible/403 "2020-01-20T18:19:04Z")

</div>

Hi! Since the introduction of the block decorator, all functions in the calltrace of a design, have to be decorated by it. This way, all these functions make a contribution to the name of its internal signals. This beha…

---

## [Could modbv support non powers of two?](https://discourse.myhdl.org/t/could-modbv-support-non-powers-of-two/351)

<div class="topic-metadata">

**Author:** [@WayneUroda](https://discourse.myhdl.org/u/WayneUroda)\
**Replies:** 10\
**Last updated:** [December 23, 2018, 3:22pm UTC](https://discourse.myhdl.org/t/could-modbv-support-non-powers-of-two/351 "2018-12-23T15:22:18Z")

</div>

I find myself very frequently writing if reg != reg.max - 1: reg.next = reg + 1 else: reg.next = 0 This seems the perfect fit for a modbv, but not yet have I actually encountered this where my max is a power of two …

---

## [Coalesce identical sequential blocks into the same block?](https://discourse.myhdl.org/t/coalesce-identical-sequential-blocks-into-the-same-block/350)

<div class="topic-metadata">

**Author:** [@WayneUroda](https://discourse.myhdl.org/u/WayneUroda)\
**Replies:** 9\
**Last updated:** [December 22, 2018, 3:04pm UTC](https://discourse.myhdl.org/t/coalesce-identical-sequential-blocks-into-the-same-block/350 "2018-12-22T15:04:45Z")

</div>

Coming from a microcontroller background, it is common to interface to a peripheral (such as a UART) and one can set a register from outside the peripheral, and internally the peripheral can clear it. I started a new de…

---

## [Conversion hierarchy extraction?](https://discourse.myhdl.org/t/conversion-hierarchy-extraction/348)

<div class="topic-metadata">

**Author:** [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Replies:** 8\
**Last updated:** [December 10, 2018, 11:24am UTC](https://discourse.myhdl.org/t/conversion-hierarchy-extraction/348 "2018-12-10T11:24:52Z")

</div>

Does someone work on hierarchy extraction in VHDL/verilog converter ?

---

## [VHDL Bit string representation](https://discourse.myhdl.org/t/vhdl-bit-string-representation/344)

<div class="topic-metadata">

**Author:** [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Replies:** 15\
**Last updated:** [November 5, 2018, 5:12pm UTC](https://discourse.myhdl.org/t/vhdl-bit-string-representation/344 "2018-11-05T17:12:16Z")

</div>

Hi, MyHDL to VHDL converter use to write bit strings in binary format. However, MyHDL generates VHDL2008 code. So instead of generating big binary bit string it would be better to generate hexadecimal bit string. For …

---

## [Formal methods and MyHDL](https://discourse.myhdl.org/t/formal-methods-and-myhdl/324)

<div class="topic-metadata">

**Author:** [@mhavu](https://discourse.myhdl.org/u/mhavu)\
**Replies:** 2\
**Last updated:** [August 29, 2018, 12:02pm UTC](https://discourse.myhdl.org/t/formal-methods-and-myhdl/324 "2018-08-29T12:02:02Z")

</div>

Is anyone using formal methods to verify their models written in MyHDL? Care to share your tools and workflow?

---

## [Add new Bool type to MyHDL?](https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281)

<div class="topic-metadata">

**Author:** [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Replies:** 9\
**Last updated:** [July 5, 2018, 5:43pm UTC](https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281 "2018-07-05T17:43:15Z")

</div>

Hi, While designing modules using bool signals asserted high and others asserted low, I thought it could be a good idea to create a new Bool() type where the polarity is internally managed. Like with ResetSignal(). For…

---

## [Matching a signal against a bitvector](https://discourse.myhdl.org/t/matching-a-signal-against-a-bitvector/274)

<div class="topic-metadata">

**Author:** [@theller](https://discourse.myhdl.org/u/theller)\
**Replies:** 9\
**Last updated:** [July 1, 2018, 7:30pm UTC](https://discourse.myhdl.org/t/matching-a-signal-against-a-bitvector/274 "2018-07-01T19:30:14Z")

</div>

In VHDL I sometimes used this way to match a signal against a pattern specified in a bitvector: signal mysig : std\_logic\_vector(7 downto 0); … if mysig = “01-1----” then … I find it much easier to read and understa…

---

## [Sort signal declarations in generated VHDL](https://discourse.myhdl.org/t/sort-signal-declarations-in-generated-vhdl/224)

<div class="topic-metadata">

**Author:** [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Replies:** 3\
**Last updated:** [October 5, 2017, 2:10pm UTC](https://discourse.myhdl.org/t/sort-signal-declarations-in-generated-vhdl/224 "2017-10-05T14:10:15Z")

</div>

Hi, Currently, each time a python source file is converted to VHDL, signal declarations are in a different order. I propose to sort signal declarations in generated VHDL to always get the same order. The reason why is…

---

## [Add support for nested functions](https://discourse.myhdl.org/t/add-support-for-nested-functions/198)

<div class="topic-metadata">

**Author:** [@mario](https://discourse.myhdl.org/u/mario)\
**Replies:** 4\
**Last updated:** [June 21, 2017, 1:19pm UTC](https://discourse.myhdl.org/t/add-support-for-nested-functions/198 "2017-06-21T13:19:48Z")

</div>

Hi, unlike mentioned by josyb here MyHDL's converters do not seem to support nested functions. Example code: from \_\_future\_\_ import print\_function from myhdl import \* def State\_add(x, y): return x + y def Stat…

---

## [Making cosimulation more user friendly](https://discourse.myhdl.org/t/making-cosimulation-more-user-friendly/136)

<div class="topic-metadata">

**Author:** [@jck](https://discourse.myhdl.org/u/jck)\
**Replies:** 2\
**Last updated:** [April 26, 2017, 4:29pm UTC](https://discourse.myhdl.org/t/making-cosimulation-more-user-friendly/136 "2017-04-26T16:29:46Z")

</div>

Currently, cosimulating verilog code requires a stub testbench. This is not a problem for modules generated by MyHDL, but it makes cosimulating arbitrary modules inconvenient. I think we can eliminate the need for the st…

---

## [On the design of state-machines](https://discourse.myhdl.org/t/on-the-design-of-state-machines/178)

<div class="topic-metadata">

**Author:** [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Replies:** 3\
**Last updated:** [April 5, 2017, 9:52am UTC](https://discourse.myhdl.org/t/on-the-design-of-state-machines/178 "2017-04-05T09:52:04Z")

</div>

Introduction Over the last year I have been prototyping various embedded systems and I have used FPGAs for rapid development where many developers would use micro-controllers. With Python/MyHDL this has worked very well…

---

## [Generating hierarchical VHDL](https://discourse.myhdl.org/t/generating-hierarchical-vhdl/159)

<div class="topic-metadata">

**Author:** [@lamazavr](https://discourse.myhdl.org/u/lamazavr)\
**Replies:** 1\
**Last updated:** [March 2, 2017, 3:32pm UTC](https://discourse.myhdl.org/t/generating-hierarchical-vhdl/159 "2017-03-02T15:32:52Z")

</div>

Hi, I am very new to MyHDL. I am trying to generate VHDL code from examples according to “Conversion examples” topic from documentation. Is it possible to generate separate entities for each design block instead of proc…

---

## [Instanciate undefined Signal()](https://discourse.myhdl.org/t/instanciate-undefined-signal/131)

<div class="topic-metadata">

**Author:** [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Replies:** 8\
**Last updated:** [October 20, 2016, 7:54am UTC](https://discourse.myhdl.org/t/instanciate-undefined-signal/131 "2016-10-20T07:54:55Z")

</div>

Unlike VHDL, myhdl module signals are defined outside modules. def module1(i\_clk, o\_data) : ... def module2(i\_clk, i\_data) : ... def module3() : i\_clk = Signal(bool(0)) data = Signal(bool(0)) …

---

## [Intbv and the .next attribute](https://discourse.myhdl.org/t/intbv-and-the-next-attribute/128)

<div class="topic-metadata">

**Author:** [@devbisme](https://discourse.myhdl.org/u/devbisme)\
**Replies:** 2\
**Last updated:** [October 17, 2016, 1:40pm UTC](https://discourse.myhdl.org/t/intbv-and-the-next-attribute/128 "2016-10-17T13:40:01Z")

</div>

I was doing a testbench and had a “signal” I defined as opcode = intbv('000'). Then I did something like this: opcode.next = 1 but opcode never changed during the simulation and I never got any warnings or errors. Of …

---

## [Conflict: print()](https://discourse.myhdl.org/t/conflict-print/99)

<div class="topic-metadata">

**Author:** [@josyb](https://discourse.myhdl.org/u/josyb)\
**Replies:** 5\
**Last updated:** [June 23, 2016, 2:58pm UTC](https://discourse.myhdl.org/t/conflict-print/99 "2016-06-23T14:58:10Z")

</div>

Yesterday I was debugging a test-bench. I do that with print-statements (old-school?). But complying with peer-pressure I use the Python 3 print(), with the parenthesis. Unfortunately MyHDL treats this as an HDL statemen…