MyHDL

Support


FAQ This category addresses frequently asked questions [FAQ], see also the myhdl.org FAQ page Bug The category is applied to support questions that could be bugs (and not limitations). Tests should be created for all topics with the Bug category and a pull-request generated.
Topic Replies Activity
About the Support category 1 May 15, 2016
Initial values, memories, and Yosys 3 October 21, 2019
Another MyHDL VHDL conversion bug
Bug
14 October 17, 2019
Mutiple traces/simulations in one run 5 October 13, 2019
How can I use lists of signals and still convert to verilog 13 September 18, 2019
Conversion problem with shadow signal 9 September 3, 2019
Unexpected signal name in converted VHDL 5 August 1, 2019
How to dynamically infer ports? 7 August 1, 2019
Large memory consumption 14 May 14, 2019
Preserve hierarchy 6 May 11, 2019
Vendor specific instance simulation 2 April 19, 2019
Conversion naming issue 9 April 5, 2019
Verilog conversion to write results to a file? 13 April 4, 2019
Don't care / unknown 5 March 28, 2019
Function not converting, but deflated code does 9 March 23, 2019
How to simulate for the ROM type design 18 March 12, 2019
'tuple' object has no attribute 'config_sim' 2 February 25, 2019
Changing testbench inputs during a simulation 9 February 13, 2019
Instantiating FPGA components 8 February 2, 2019
Combinational tree like accumulatioin 7 December 10, 2018
Cosimulation myhdl.vpi search path 3 November 8, 2018
VHDL constant value overflow
Bug
16 November 5, 2018
Using standart Python modules 3 October 10, 2018
Verilog width expansion and reduction operator equivalence? 3 October 6, 2018
Invoke Verilog generate for Python list handling 2 October 1, 2018
How to use counters similiar to verilog using for loops? 11 September 25, 2018
Variables in VHDL conversion
Bug
16 September 5, 2018
I don't get how to convert to VHDL 4 September 3, 2018
From myHDL to syntesis 9 August 7, 2018
Is it sensible to yield a delay of zero? 4 August 1, 2018