# Support **URL:** https://discourse.myhdl.org/c/support/5.md?page=2 [Latest](https://discourse.myhdl.org/latest.md) · [Categories](https://discourse.myhdl.org/categories.md) **Page:** 3 --- ## [How to use counters similiar to verilog using for loops?](https://discourse.myhdl.org/t/how-to-use-counters-similiar-to-verilog-using-for-loops/331)

**Author:** [@krs](https://discourse.myhdl.org/u/krs)\ **Replies:** 10\ **Last updated:** [September 25, 2018, 6:32pm UTC](https://discourse.myhdl.org/t/how-to-use-counters-similiar-to-verilog-using-for-loops/331 "2018-09-25T18:32:28Z")

Hello, I have to instantiate a chain of counters and how i do it currently is as below: NB\_CHAIN\_COUNTERS=2 def dq\_proc(clk,q,d): @always(clk) def dq\_process(): q.next = d return dq\_process data\_in\_sig\_inst=\[None… --- ## [Variables in VHDL conversion](https://discourse.myhdl.org/t/variables-in-vhdl-conversion/327)

**Author:** [@mhavu](https://discourse.myhdl.org/u/mhavu)\ **Replies:** 15\ **Last updated:** [September 5, 2018, 2:27pm UTC](https://discourse.myhdl.org/t/variables-in-vhdl-conversion/327 "2018-09-05T14:27:27Z")

Consider the following MyHDL code: @always\_comb def add(): bx\_sum = bx\[0\].signed() + bx\[1\].signed() + bx\[2\].signed() ay\_sum = ay\[0\].signed() + ay\[1\].signed() result.next = (bx\_sum \<\< BX\_SHIFT) - (ay\_sum \<\< A… --- ## [I don't get how to convert to VHDL](https://discourse.myhdl.org/t/i-dont-get-how-to-convert-to-vhdl/329)

**Author:** [@L\_A](https://discourse.myhdl.org/u/L_A)\ **Replies:** 3\ **Last updated:** [September 3, 2018, 2:40pm UTC](https://discourse.myhdl.org/t/i-dont-get-how-to-convert-to-vhdl/329 "2018-09-03T14:40:46Z")

I was thinking, there should be a program called myhdl working like: $ myhdl vhdl hello1.py …converted to VHDL: hello1.vhd I know the link: http://docs.myhdl.org/en/stable/manual/conversion.html I read the full page… --- ## [From myHDL to syntesis](https://discourse.myhdl.org/t/from-myhdl-to-syntesis/323)

**Author:** [@mngr](https://discourse.myhdl.org/u/mngr)\ **Replies:** 8\ **Last updated:** [August 7, 2018, 8:33am UTC](https://discourse.myhdl.org/t/from-myhdl-to-syntesis/323 "2018-08-07T08:33:10Z")

Hi everyone, I am very new in the FGPA world, and I am making the first steps. I have a little myHDL program and I am trying to synthesize it. (converting to Verilog, then using icestorm) the simulation works as inten… --- ## [Is it sensible to yield a delay of zero?](https://discourse.myhdl.org/t/is-it-sensible-to-yield-a-delay-of-zero/317)

**Author:** [@meowsqueak](https://discourse.myhdl.org/u/meowsqueak)\ **Replies:** 3\ **Last updated:** [August 1, 2018, 9:44am UTC](https://discourse.myhdl.org/t/is-it-sensible-to-yield-a-delay-of-zero/317 "2018-08-01T09:44:48Z")

I’m writing a unit test for some simple MyHDL and I’d like to know if it’s valid to call yield delay(0) at the start of a test generator in order to make a combinatorial @always\_comb evaluate its outputs? If I don’t do t… --- ## [VHDL conversion - missing constant](https://discourse.myhdl.org/t/vhdl-conversion-missing-constant/318)

**Author:** [@meowsqueak](https://discourse.myhdl.org/u/meowsqueak)\ **Replies:** 3\ **Last updated:** [July 31, 2018, 7:08am UTC](https://discourse.myhdl.org/t/vhdl-conversion-missing-constant/318 "2018-07-31T07:08:42Z")

I’m finding my way around MyHDL. I’m well-versed in VHDL and experienced with Python, but as another post mentioned recently, there’s an open-source toolchain for Lattice FPGAs but it only supports Verilog, so I’m lookin… --- ## [Convert FROM vhdl](https://discourse.myhdl.org/t/convert-from-vhdl/313)

**Author:** [@mngr](https://discourse.myhdl.org/u/mngr)\ **Replies:** 1\ **Last updated:** [July 20, 2018, 11:36am UTC](https://discourse.myhdl.org/t/convert-from-vhdl/313 "2018-07-20T11:36:46Z")

Hi everyone, I am very new here, an I would like to ask a couple a question: I am currently working on a project done in VHDL, and I want to port it to the open source toolchain made for Lattice FPGA. for what I know,… --- ## [Requirement: 800+ function inputs/outputs (pinmux)](https://discourse.myhdl.org/t/requirement-800-function-inputs-outputs-pinmux/282)

**Author:** [@lkcl](https://discourse.myhdl.org/u/lkcl)\ **Replies:** 17\ **Last updated:** [July 10, 2018, 8:13pm UTC](https://discourse.myhdl.org/t/requirement-800-function-inputs-outputs-pinmux/282 "2018-07-10T20:13:48Z")

so whilst that may sound completely and utterly insane, to have a python (verilog) function with over 800 inputs and outputs, for a pinmux that’s on the reasonable side. background: i am currently designing a libre pinm… --- ## [Explicitly listing instances and instances() give different output (solved)](https://discourse.myhdl.org/t/explicitly-listing-instances-and-instances-give-different-output-solved/276)

**Author:** [@mhavu](https://discourse.myhdl.org/u/mhavu)\ **Replies:** 2\ **Last updated:** [June 4, 2018, 1:05pm UTC](https://discourse.myhdl.org/t/explicitly-listing-instances-and-instances-give-different-output-solved/276 "2018-06-04T13:05:00Z")

In the following code, if I use instances() in the testbench, everything works as expected. If I return the instances by listing them explicitly, fall and rise stay low no matter what I do. (I can even explicitly say ris… --- ## [Conversion of list of objects](https://discourse.myhdl.org/t/conversion-of-list-of-objects/275)

**Author:** [@aurang](https://discourse.myhdl.org/u/aurang)\ **Replies:** 1\ **Last updated:** [June 1, 2018, 3:55pm UTC](https://discourse.myhdl.org/t/conversion-of-list-of-objects/275 "2018-06-01T15:55:27Z")

I have following class. class framegrabber\_roi(): def init(self, nb\_bits\_roi=16): if not 16 == nb\_bits\_roi: raise ValueError(“Number of bits to represent ROI must be 16”) self.roi\_width = Signal(intbv(0)\[n… --- ## [Instances are renamed every time in MyHDL 0.10](https://discourse.myhdl.org/t/instances-are-renamed-every-time-in-myhdl-0-10/272)

**Author:** [@mhavu](https://discourse.myhdl.org/u/mhavu)\ **Replies:** 3\ **Last updated:** [May 4, 2018, 9:42am UTC](https://discourse.myhdl.org/t/instances-are-renamed-every-time-in-myhdl-0-10/272 "2018-05-04T09:42:50Z")

I just upgraded to MyHDL 0.10 and the new API. This fixed a couple of issues I had, but also caused a new one: I get “ToVHDLWarning: Previously used name being reused” warnings every time I rerun conversion. In simulatio… --- ## [Instance-specific constants in VHDL conversion](https://discourse.myhdl.org/t/instance-specific-constants-in-vhdl-conversion/262)

**Author:** [@mhavu](https://discourse.myhdl.org/u/mhavu)\ **Replies:** 16\ **Last updated:** [April 16, 2018, 11:46am UTC](https://discourse.myhdl.org/t/instance-specific-constants-in-vhdl-conversion/262 "2018-04-16T11:46:42Z")

My module computes some constants based on the bit widths of the signals. In my design I have several instances of this module. In simulation, each instance seems to get the correct constants. However, when converting to… --- ## [Porting out a list of 8 bools as an 8-bit vector](https://discourse.myhdl.org/t/porting-out-a-list-of-8-bools-as-an-8-bit-vector/270)

**Author:** [@kc64](https://discourse.myhdl.org/u/kc64)\ **Replies:** 6\ **Last updated:** [April 13, 2018, 9:15am UTC](https://discourse.myhdl.org/t/porting-out-a-list-of-8-bools-as-an-8-bit-vector/270 "2018-04-13T09:15:30Z")

I have a port on my design that I wish to output as an 8-bit vector called trigger\_outputs. My outputs list is an 8-element entity. How do I define a connection between the port and the list? --- ## [Grabbing a bit from a configuration register](https://discourse.myhdl.org/t/grabbing-a-bit-from-a-configuration-register/269)

**Author:** [@kc64](https://discourse.myhdl.org/u/kc64)\ **Replies:** 2\ **Last updated:** [April 10, 2018, 1:49pm UTC](https://discourse.myhdl.org/t/grabbing-a-bit-from-a-configuration-register/269 "2018-04-10T13:49:25Z")

I’ve instantiated an array of 32-bit registers and have stored a value in bit 0 of register 0. I wish to use that bit to control my counter but have not succeeded. My code includes period\_counter = counter(reset=reset… --- ## [myhdl.AlwaysCombError: signal used as inout in always\_comb function argument](https://discourse.myhdl.org/t/myhdl-alwayscomberror-signal-used-as-inout-in-always-comb-function-argument/268)

**Author:** [@Robert\_Baruch](https://discourse.myhdl.org/u/Robert_Baruch)\ **Replies:** 3\ **Last updated:** [April 10, 2018, 2:35am UTC](https://discourse.myhdl.org/t/myhdl-alwayscomberror-signal-used-as-inout-in-always-comb-function-argument/268 "2018-04-10T02:35:57Z")

I’m new to myHDL and VDHL. I’m trying to duplicate the combinatorial logic of a 74154 4:16 decoder. When I run my unit test, I get this error: testDisable (\_\_main\_\_.TestLVC154) ... ERROR ===============================… --- ## [Inverting a signal passed into a module](https://discourse.myhdl.org/t/inverting-a-signal-passed-into-a-module/266)

**Author:** [@kc64](https://discourse.myhdl.org/u/kc64)\ **Replies:** 2\ **Last updated:** [April 5, 2018, 6:34pm UTC](https://discourse.myhdl.org/t/inverting-a-signal-passed-into-a-module/266 "2018-04-05T18:34:54Z")

When I use the form ff\_1 = dffe(reset, clock, d, q, ena) I get the expected results. But when I do this ff\_1 = dffe(reset, clock, d, q, not ena) or ff\_1 = dffe(reset, clock, d, q, not(ena)) I get ToVerilogWarning… --- ## [Biquad filter produces garbage (solved)](https://discourse.myhdl.org/t/biquad-filter-produces-garbage-solved/261)

**Author:** [@mhavu](https://discourse.myhdl.org/u/mhavu)\ **Replies:** 6\ **Last updated:** [April 5, 2018, 7:15am UTC](https://discourse.myhdl.org/t/biquad-filter-produces-garbage-solved/261 "2018-04-05T07:15:19Z")

I’ve been having trouble with the stability of my biquad filter implementation for quite some time now. Today I finally created the following minimal test to find out what is going on. For some reason, looping with biqua… --- ## [Connecting signals between modules](https://discourse.myhdl.org/t/connecting-signals-between-modules/265)

**Author:** [@kc64](https://discourse.myhdl.org/u/kc64)\ **Replies:** 2\ **Last updated:** [April 4, 2018, 10:14pm UTC](https://discourse.myhdl.org/t/connecting-signals-between-modules/265 "2018-04-04T22:14:24Z")

I’ve come to the conclusion that I apparently don’t have a clue how to connect signals between modules. As an example, I have made a DFFE module which I can simualte and convert to V\*. When I try to connect two of thes… --- ## [Exception raised on reset signal](https://discourse.myhdl.org/t/exception-raised-on-reset-signal/264)

**Author:** [@kc64](https://discourse.myhdl.org/u/kc64)\ **Replies:** 6\ **Last updated:** [April 4, 2018, 8:44am UTC](https://discourse.myhdl.org/t/exception-raised-on-reset-signal/264 "2018-04-04T08:44:11Z")

I’m stalled trying to figure out the cause of this exception. I’ve tried following the FSM example in the user manual and I think it looks real close but that one runs and mine does not. Can anyone spot what I’ve done … --- ## [Moving to 0.1dev broke my design](https://discourse.myhdl.org/t/moving-to-0-1dev-broke-my-design/259)

**Author:** [@kc64](https://discourse.myhdl.org/u/kc64)\ **Replies:** 1\ **Last updated:** [March 23, 2018, 10:23am UTC](https://discourse.myhdl.org/t/moving-to-0-1dev-broke-my-design/259 "2018-03-23T10:23:28Z")

I updated my version of MyHDL and my code broke. It looks like conversion to .v worked but the test/simulation failed. After spending hours on the forums, I have not recovered that part yet. This is what worked end-to-… --- ## [Iterating over a group of elements](https://discourse.myhdl.org/t/iterating-over-a-group-of-elements/258)

**Author:** [@kc64](https://discourse.myhdl.org/u/kc64)\ **Replies:** 3\ **Last updated:** [March 22, 2018, 3:35pm UTC](https://discourse.myhdl.org/t/iterating-over-a-group-of-elements/258 "2018-03-22T15:35:54Z")

I am designing an interface that implements an 8-bit-to-32-bit register. Upon clear or reset, I want to reset the byte value registers to 0. I hoped to do this using an elegant approach but have only succeeded with som… --- ## [Multi-bit latch](https://discourse.myhdl.org/t/multi-bit-latch/257)

**Author:** [@kc64](https://discourse.myhdl.org/u/kc64)\ **Replies:** 4\ **Last updated:** [March 22, 2018, 4:03am UTC](https://discourse.myhdl.org/t/multi-bit-latch/257 "2018-03-22T04:03:33Z")

I’m new to MyHDL and trying to implement a simple design as a learning exercise. I am following the latch design in the examples but when I attempt to make it 8-bits wide (like a 74373), I have troubles. Are there any … --- ## [Py.test fails on Ubuntu 16.04](https://discourse.myhdl.org/t/py-test-fails-on-ubuntu-16-04/250)

**Author:** [@legendbb](https://discourse.myhdl.org/u/legendbb)\ **Replies:** 2\ **Last updated:** [February 10, 2018, 1:15am UTC](https://discourse.myhdl.org/t/py-test-fails-on-ubuntu-16-04/250 "2018-02-10T01:15:20Z")

myHDL 1.0 dev version has no issue on MacOSX with Python 2.7.10 But on Ubuntu 16.04 with default python3.5.2; didn’t figure out how to run py.test of python 3.6. py.test fails with error message: myhdl.CosimulationErr… --- ## [Verilog generate for always blocks in myhdl](https://discourse.myhdl.org/t/verilog-generate-for-always-blocks-in-myhdl/246)

**Author:** [@aurang](https://discourse.myhdl.org/u/aurang)\ **Replies:** 4\ **Last updated:** [January 22, 2018, 7:16pm UTC](https://discourse.myhdl.org/t/verilog-generate-for-always-blocks-in-myhdl/246 "2018-01-22T19:16:57Z")

Hi, is it possible to write code in myhdl which serves the same purpose as “generate” keyword in Verilog for always blocks. Does the converted code then represents the correct hardware behavior. I did not find any exa… --- ## [Conversion producing invalid register names](https://discourse.myhdl.org/t/conversion-producing-invalid-register-names/242)

**Author:** [@romanenkor](https://discourse.myhdl.org/u/romanenkor)\ **Replies:** 9\ **Last updated:** [January 5, 2018, 2:24pm UTC](https://discourse.myhdl.org/t/conversion-producing-invalid-register-names/242 "2018-01-05T14:24:19Z")

Hello, everybody. I have been trying to create a bus arbiter module to externally set an “access granted” flag for each device in a list. I ended up writing following code: #bus.py from myhdl import \* # Grants access t… --- ## [\[FAQ\] Contributing to MyHDL](https://discourse.myhdl.org/t/faq-contributing-to-myhdl/239)

**Author:** [@cfelton](https://discourse.myhdl.org/u/cfelton)\ **Replies:** 0\ **Last updated:** [November 10, 2017, 4:36pm UTC](https://discourse.myhdl.org/t/faq-contributing-to-myhdl/239 "2017-11-10T16:36:06Z")

A frequent question and comment is how can I contribute to the myhdl project. One of the best ways for a new user to contribute, is to create a blog or website to showcase user generated examples and projects. One of t… --- ## [Issues and PRs are piling up](https://discourse.myhdl.org/t/issues-and-prs-are-piling-up/167)

**Author:** [@hashhsah](https://discourse.myhdl.org/u/hashhsah)\ **Replies:** 4\ **Last updated:** [November 6, 2017, 3:08pm UTC](https://discourse.myhdl.org/t/issues-and-prs-are-piling-up/167 "2017-11-06T15:08:58Z")

Our project hit a few bugs that can be fixed by some of the pending PRs, e.g. by https://github.com/myhdl/myhdl/pull/189 . With jandecaluwe the BDFL of myhdl busy with other projects, I'm wondering if there is an inte… --- ## [Signals in objects vs. function arguments or method calls](https://discourse.myhdl.org/t/signals-in-objects-vs-function-arguments-or-method-calls/237)

**Author:** [@jsyk](https://discourse.myhdl.org/u/jsyk)\ **Replies:** 8\ **Last updated:** [November 1, 2017, 10:26am UTC](https://discourse.myhdl.org/t/signals-in-objects-vs-function-arguments-or-method-calls/237 "2017-11-01T10:26:50Z")

Hello, I am new to MyHDL and trying to understand what’s possible to do with it compared to VHDL. In the past I did some work in VHDL on FPGAs. My question: I want to put signals into objects and use them as interfaces… --- ## [Testbench conversion (solved)](https://discourse.myhdl.org/t/testbench-conversion-solved/233)

**Author:** [@pythondsp](https://discourse.myhdl.org/u/pythondsp)\ **Replies:** 11\ **Last updated:** [October 16, 2017, 6:10pm UTC](https://discourse.myhdl.org/t/testbench-conversion-solved/233 "2017-10-16T18:10:21Z")

In the below, a Mod-m counter is implemented along with testbench. http://fpga-designs-with-myhdl.readthedocs.io/en/latest/myhdl/testbench.html#mod-m-counter Is it possible to convert the MyHDL testbench to HDL testbe… --- ## [Saving testbench data to file (solved)](https://discourse.myhdl.org/t/saving-testbench-data-to-file-solved/234)

**Author:** [@pythondsp](https://discourse.myhdl.org/u/pythondsp)\ **Replies:** 2\ **Last updated:** [October 16, 2017, 6:42am UTC](https://discourse.myhdl.org/t/saving-testbench-data-to-file-solved/234 "2017-10-16T06:42:39Z")

In the below link, I tried to saved the simulation-data in the file. Do you have any suggestion for this, or is it fine? This looks fine to me, but need advice as I am new to MyHDL (only 10 days experience). http://fp… [Previous page](https://discourse.myhdl.org/c/support/5.md?page=1) [Next page](https://discourse.myhdl.org/c/support/5.md?page=3)