# Support

**URL:** https://discourse.myhdl.org/c/support/5.md?page=4

[Latest](https://discourse.myhdl.org/latest.md) · [Categories](https://discourse.myhdl.org/categories.md)

**Page:** 5

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## [Problem while converting to VHDL code](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89)

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**Author:** [@Ravi\_Jain](https://discourse.myhdl.org/u/Ravi_Jain)\
**Replies:** 14\
**Last updated:** [June 16, 2016, 8:09pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89 "2016-06-16T20:09:36Z")

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While verifying converted output into verilog and vhdl sequentially as in below, it causes problems. def test\_convertible(): @block def test(): hostmanagement\_interface = HostManagementInterface() mdio\_interfa…

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## [Error in the converted verilog code](https://discourse.myhdl.org/t/error-in-the-converted-verilog-code/88)

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**Author:** [@Ravi\_Jain](https://discourse.myhdl.org/u/Ravi_Jain)\
**Replies:** 8\
**Last updated:** [June 16, 2016, 5:59pm UTC](https://discourse.myhdl.org/t/error-in-the-converted-verilog-code/88 "2016-06-16T17:59:36Z")

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1.In the converted code, On reset the initial values are assigned improperly. MyHDL snippet: self.rdindex = Signal(intbv(17, min=0, max=18)) self.wrindex = Signal(intbv(62, min=0, max=63)) Verilog code snip…

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## [A minor flaw when using the new API](https://discourse.myhdl.org/t/a-minor-flaw-when-using-the-new-api/85)

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**Author:** [@josyb](https://discourse.myhdl.org/u/josyb)\
**Replies:** 2\
**Last updated:** [June 10, 2016, 11:05am UTC](https://discourse.myhdl.org/t/a-minor-flaw-when-using-the-new-api/85 "2016-06-10T11:05:06Z")

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Using Eclipse with Pylint: inst = top\_upcounter(C\_COUNT\_BITS, Clk, Reset, SClr, CntEn, CountMax, Q, IsMaxMinusOne, IsMax) inst.convert('VHDL') gets flagged with : Instance of 'list' has no 'convert' memb…

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## [ToVHDLWarning: Port is not used:](https://discourse.myhdl.org/t/tovhdlwarning-port-is-not-used/80)

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**Author:** [@josyb](https://discourse.myhdl.org/u/josyb)\
**Replies:** 2\
**Last updated:** [June 6, 2016, 6:59pm UTC](https://discourse.myhdl.org/t/tovhdlwarning-port-is-not-used/80 "2016-06-06T18:59:24Z")

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While experimenting I got faced with this warning, and I can't find out why ... from \_\_future\_\_ import print\_function from myhdl import Signal, intbv, always\_seq, always\_comb, block @block def fmux(Clk, Reset, Da…

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## [PyDev-Eclipse confuses with async](https://discourse.myhdl.org/t/pydev-eclipse-confuses-with-async/51)

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**Author:** [@Ravi\_Jain](https://discourse.myhdl.org/u/Ravi_Jain)\
**Replies:** 10\
**Last updated:** [June 2, 2016, 5:32pm UTC](https://discourse.myhdl.org/t/pydev-eclipse-confuses-with-async/51 "2016-06-02T17:32:25Z")

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The PyDev - Eclipse IDE on Windows platform shows a problem while instantiating ResetSignal. It confuses with the keyword async introduced newly in the Python 3.5 semantics. It doesn't create a problem during runtime. Bu…

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## [Unexpected Output with Default parameters](https://discourse.myhdl.org/t/unexpected-output-with-default-parameters/44)

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**Author:** [@sriramesh4](https://discourse.myhdl.org/u/sriramesh4)\
**Replies:** 8\
**Last updated:** [May 28, 2016, 1:32am UTC](https://discourse.myhdl.org/t/unexpected-output-with-default-parameters/44 "2016-05-28T01:32:43Z")

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This sample code here produces an output waveform which is same for both the signals 'sig' of the instances 'a' and 'b'. This happens only when I use the default parameter(In this example value for 'sig' is not passed w…

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## [Problem with vcd output](https://discourse.myhdl.org/t/problem-with-vcd-output/39)

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**Author:** [@sriramesh4](https://discourse.myhdl.org/u/sriramesh4)\
**Replies:** 2\
**Last updated:** [May 24, 2016, 10:25am UTC](https://discourse.myhdl.org/t/problem-with-vcd-output/39 "2016-05-24T10:25:29Z")

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The code in the gist creates a vcd file which when opened using GTKwave shows some undesired waveform. https://gist.github.com/srivatsan-ramesh/ed9b2106b42c3a6f9f82a8bc86b5454e Here in this example both 'ins1' and 'i…

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