# Bug **URL:** https://discourse.myhdl.org/c/support/bug/9.md [Latest](https://discourse.myhdl.org/latest.md) · [Categories](https://discourse.myhdl.org/categories.md) --- ## [About the Bug category](https://discourse.myhdl.org/t/about-the-bug-category/123)
**Author:** [@cfelton](https://discourse.myhdl.org/u/cfelton)\ **Replies:** 0
The category is applied to support questions that could be bugs (and not limitations). Tests should be created for all topics with the Bug category and a pull-request generated. --- ## [VHDL constant value overflow](https://discourse.myhdl.org/t/vhdl-constant-value-overflow/326)
**Author:** [@mhavu](https://discourse.myhdl.org/u/mhavu)\ **Replies:** 16\ **Last updated:** [July 24, 2024, 10:35am UTC](https://discourse.myhdl.org/t/vhdl-constant-value-overflow/326 "2024-07-24T10:35:02Z")
How do MyHDL people usually work around the VHDL size limit for integer literals? Consider the following MyHDL code: Y\_LEN = 71 Y\_MIN, Y\_MAX = (-2\*\*(Y\_LEN - 1), 2\*\*(Y\_LEN - 1)) y = Signal(intbv(0, Y\_MIN, Y\_MAX)) # An a… --- ## [I am having issue, when i am converting myhdl to verilog it gives me error on list indexing](https://discourse.myhdl.org/t/i-am-having-issue-when-i-am-converting-myhdl-to-verilog-it-gives-me-error-on-list-indexing/481)
**Author:** [@nameer](https://discourse.myhdl.org/u/nameer)\ **Replies:** 0\ **Last updated:** [November 29, 2021, 10:47am UTC](https://discourse.myhdl.org/t/i-am-having-issue-when-i-am-converting-myhdl-to-verilog-it-gives-me-error-on-list-indexing/481 "2021-11-29T10:47:08Z")
Support questions that have been identified as possible bugs. A test case needs to be created for each of these and a merge request created to the myhdl repository. here is the code \` from myhdl import \* import arra… --- ## [Another MyHDL VHDL conversion bug](https://discourse.myhdl.org/t/another-myhdl-vhdl-conversion-bug/393)
**Author:** [@ThomasHornschuh](https://discourse.myhdl.org/u/ThomasHornschuh)\ **Replies:** 13\ **Last updated:** [October 17, 2019, 12:15am UTC](https://discourse.myhdl.org/t/another-myhdl-vhdl-conversion-bug/393 "2019-10-17T00:15:54Z")
The following line self.res\_o.next = concat( modbv(0)\[31:\], self.op1\_i \< self.op2\_i ) is converted to this VHDL code: self\_res\_o\_num \<= unsigned'(unsigned'("0000000000000000000000000000000") & (self\_op1\_i\_num \< self\_… --- ## [Variables in VHDL conversion](https://discourse.myhdl.org/t/variables-in-vhdl-conversion/327)
**Author:** [@mhavu](https://discourse.myhdl.org/u/mhavu)\ **Replies:** 15\ **Last updated:** [September 5, 2018, 2:27pm UTC](https://discourse.myhdl.org/t/variables-in-vhdl-conversion/327 "2018-09-05T14:27:27Z")
Consider the following MyHDL code: @always\_comb def add(): bx\_sum = bx\[0\].signed() + bx\[1\].signed() + bx\[2\].signed() ay\_sum = ay\[0\].signed() + ay\[1\].signed() result.next = (bx\_sum \<\< BX\_SHIFT) - (ay\_sum \<\< A… --- ## [Explicitly listing instances and instances() give different output (solved)](https://discourse.myhdl.org/t/explicitly-listing-instances-and-instances-give-different-output-solved/276)
**Author:** [@mhavu](https://discourse.myhdl.org/u/mhavu)\ **Replies:** 2\ **Last updated:** [June 4, 2018, 1:05pm UTC](https://discourse.myhdl.org/t/explicitly-listing-instances-and-instances-give-different-output-solved/276 "2018-06-04T13:05:00Z")
In the following code, if I use instances() in the testbench, everything works as expected. If I return the instances by listing them explicitly, fall and rise stay low no matter what I do. (I can even explicitly say ris… --- ## [Instances are renamed every time in MyHDL 0.10](https://discourse.myhdl.org/t/instances-are-renamed-every-time-in-myhdl-0-10/272)
**Author:** [@mhavu](https://discourse.myhdl.org/u/mhavu)\ **Replies:** 3\ **Last updated:** [May 4, 2018, 9:42am UTC](https://discourse.myhdl.org/t/instances-are-renamed-every-time-in-myhdl-0-10/272 "2018-05-04T09:42:50Z")
I just upgraded to MyHDL 0.10 and the new API. This fixed a couple of issues I had, but also caused a new one: I get “ToVHDLWarning: Previously used name being reused” warnings every time I rerun conversion. In simulatio… --- ## [Testbench conversion (solved)](https://discourse.myhdl.org/t/testbench-conversion-solved/233)
**Author:** [@pythondsp](https://discourse.myhdl.org/u/pythondsp)\ **Replies:** 11\ **Last updated:** [October 16, 2017, 6:10pm UTC](https://discourse.myhdl.org/t/testbench-conversion-solved/233 "2017-10-16T18:10:21Z")
In the below, a Mod-m counter is implemented along with testbench. http://fpga-designs-with-myhdl.readthedocs.io/en/latest/myhdl/testbench.html#mod-m-counter Is it possible to convert the MyHDL testbench to HDL testbe… --- ## [VHDL conversion bug (resize of signed signal)?](https://discourse.myhdl.org/t/vhdl-conversion-bug-resize-of-signed-signal/225)
**Author:** [@DrPi](https://discourse.myhdl.org/u/DrPi)\ **Replies:** 4\ **Last updated:** [October 5, 2017, 2:48pm UTC](https://discourse.myhdl.org/t/vhdl-conversion-bug-resize-of-signed-signal/225 "2017-10-05T14:48:25Z")
Before submitting a bug I’d like to check my assumptions are correct. I have the following in a design : def AudioSample(reset\_value=0, nb\_bits=24): return intbv(0, min=-(2\*\*(nb\_bits-1)), max=2\*\*(nb\_bits-1)) #… --- ## [Weird register behavior during simulation](https://discourse.myhdl.org/t/weird-register-behavior-during-simulation/213)
**Author:** [@Nathan\_Sketch](https://discourse.myhdl.org/u/Nathan_Sketch)\ **Replies:** 2\ **Last updated:** [August 6, 2017, 11:11am UTC](https://discourse.myhdl.org/t/weird-register-behavior-during-simulation/213 "2017-08-06T11:11:02Z")
I was writing a test bench for a ps2 host transmitter and signals are sent from the device to the board. I registered the inputs, but I got some weird behavior in the simulation. If the signals come in at the same time a… --- ## [Intbv single bit modification](https://discourse.myhdl.org/t/intbv-single-bit-modification/152)
**Author:** [@DrPi](https://discourse.myhdl.org/u/DrPi)\ **Replies:** 4\ **Last updated:** [January 26, 2017, 7:27am UTC](https://discourse.myhdl.org/t/intbv-single-bit-modification/152 "2017-01-26T07:27:09Z")
Using a signal declared like this : data = Signal(intbv(0)\[4:\] I want to change only one bit of this signal in a process. For example : @always\_seq(posedge(i\_Clk), reset=None) def regs\_manager(): … --- ## [Bug #209 : work-around?](https://discourse.myhdl.org/t/bug-209-work-around/148)
**Author:** [@DrPi](https://discourse.myhdl.org/u/DrPi)\ **Replies:** 1\ **Last updated:** [January 20, 2017, 2:35pm UTC](https://discourse.myhdl.org/t/bug-209-work-around/148 "2017-01-20T14:35:12Z")
I've just added bug #209 in github. It is very annoying for the way I code. Does anyone have a work-around (except using functions instead of class method) ? --- ## [Constant bit vectors in a concat() expression](https://discourse.myhdl.org/t/constant-bit-vectors-in-a-concat-expression/121)
**Author:** [@haunma](https://discourse.myhdl.org/u/haunma)\ **Replies:** 8\ **Last updated:** [October 4, 2016, 7:21pm UTC](https://discourse.myhdl.org/t/constant-bit-vectors-in-a-concat-expression/121 "2016-10-04T19:21:18Z")
I am having difficulty with Verilog conversion of a concatenation expression: ONE = bool(1) ZERO = bool(0) EIGHT\_ZEROS = 0b1010101010101010 PREAMBLE\_B = 0b10011100 PREAMBLE\_M = 0b10010011 PREAMBLE\_W = 0b10010110 parit… --- ## [Newbie questions: trying to understand Verilog conversion behavior](https://discourse.myhdl.org/t/newbie-questions-trying-to-understand-verilog-conversion-behavior/117)
**Author:** [@haunma](https://discourse.myhdl.org/u/haunma)\ **Replies:** 2\ **Last updated:** [September 16, 2016, 2:01am UTC](https://discourse.myhdl.org/t/newbie-questions-trying-to-understand-verilog-conversion-behavior/117 "2016-09-16T02:01:04Z")
Hi everyone, I just posted this to the mailman list, then realized I should have come here instead. Should this Discourse link be added to the myhdl.org Support-\>Community page? I'm new to MyHDL, using it with a Dig…