# Uncategorized

**URL:** https://discourse.myhdl.org/c/uncategorized/1.md?page=1

[Latest](https://discourse.myhdl.org/latest.md) · [Categories](https://discourse.myhdl.org/categories.md)

**Page:** 2

---

## [Synthesisable TristateSignal](https://discourse.myhdl.org/t/synthesisable-tristatesignal/216)

<div class="topic-metadata">

**Author:** [@krbonne](https://discourse.myhdl.org/u/krbonne)\
**Replies:** 17\
**Last updated:** [September 8, 2017, 10:22pm UTC](https://discourse.myhdl.org/t/synthesisable-tristatesignal/216 "2017-09-08T22:22:57Z")

</div>

Hi, Can somebody explain how to use TristateSignal’s and create verilog that can be synthesised? If I understand the documentation correctly, this needs to be done like this: (BUS is the “bus”, io1 and io2 are two sig…

---

## [Hi every one,i like python](https://discourse.myhdl.org/t/hi-every-one-i-like-python/177)

<div class="topic-metadata">

**Author:** [@JIANXIN\_YUN](https://discourse.myhdl.org/u/JIANXIN_YUN)\
**Replies:** 1\
**Last updated:** [April 1, 2017, 6:30am UTC](https://discourse.myhdl.org/t/hi-every-one-i-like-python/177 "2017-04-01T06:30:18Z")

</div>

design digital hardware with python really cool,i love python,because this programming language very like English language itself,read or write python code just like reading/writing English

---

## [Performance comparision with systemc](https://discourse.myhdl.org/t/performance-comparision-with-systemc/141)

<div class="topic-metadata">

**Author:** [@dilawar](https://discourse.myhdl.org/u/dilawar)\
**Replies:** 1\
**Last updated:** [December 19, 2016, 9:38pm UTC](https://discourse.myhdl.org/t/performance-comparision-with-systemc/141 "2016-12-19T21:38:48Z")

</div>

Hello, I just wrote my model in python-myhdl. Each iteration takes approximately 34 seconds with python-2.7 (Ubuntu-16.04), and 24 seconds with pypy. Thanks to myhdl, it didn't take much time to write the model. I …

---

## [Intbv arithmetic operations return types](https://discourse.myhdl.org/t/intbv-arithmetic-operations-return-types/132)

<div class="topic-metadata">

**Author:** [@jck](https://discourse.myhdl.org/u/jck)\
**Replies:** 7\
**Last updated:** [November 1, 2016, 3:28pm UTC](https://discourse.myhdl.org/t/intbv-arithmetic-operations-return-types/132 "2016-11-01T15:28:12Z")

</div>

Is there any particular reason why adding or subtracting intbvs return ints, but anding, shifting etc return intvbs?

---

## [More user friendly interface and LoS names in \`v\*\_code\` blocks](https://discourse.myhdl.org/t/more-user-friendly-interface-and-los-names-in-v--code-blocks/71)

<div class="topic-metadata">

**Author:** [@hgomersall](https://discourse.myhdl.org/u/hgomersall)\
**Replies:** 1\
**Last updated:** [June 2, 2016, 4:24pm UTC](https://discourse.myhdl.org/t/more-user-friendly-interface-and-los-names-in-v--code-blocks/71 "2016-06-02T16:24:54Z")

</div>

I've implemented inside \_block.py a method for handling user code that allows more python-like naming of interface signals. It's currently a bit crude and currently only works for VHDL, but demonstrates the principle. …

---

## [New, copy, clone or duplicate?](https://discourse.myhdl.org/t/new-copy-clone-or-duplicate/31)

<div class="topic-metadata">

**Author:** [@josyb](https://discourse.myhdl.org/u/josyb)\
**Replies:** 11\
**Last updated:** [May 23, 2016, 7:32pm UTC](https://discourse.myhdl.org/t/new-copy-clone-or-duplicate/31 "2016-05-23T19:32:48Z")

</div>

We often need to declare a local Signal with the same properties as a port. I used localsignal = Signal(intbv(0)\[len(portsignal):\]) but this only works for intbv types. Chris taught me: localsignal = Signal(portsignal.\_v…

[Previous page](https://discourse.myhdl.org/c/uncategorized/1.md)