# Latest

**URL:** https://discourse.myhdl.org/latest.md

[Latest](https://discourse.myhdl.org/latest.md) · [Categories](https://discourse.myhdl.org/categories.md)

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## [Welcome to the MyHDL Discussion forum!](https://discourse.myhdl.org/t/welcome-to-the-myhdl-discussion-forum/8)

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**Author:** [@system](https://discourse.myhdl.org/u/system)\
**Replies:** 0\
**Last updated:** [May 15, 2016, 12:25pm UTC](https://discourse.myhdl.org/t/welcome-to-the-myhdl-discussion-forum/8 "2016-05-15T12:25:39Z")

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We're running on the open source Discourse forum software. They are also providing the hosting for us. Thanks guys! Please this space as a place to talk about building stuff using MyHDL, best practices, and ideas for d…

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## [Conditional conversion tricks?](https://discourse.myhdl.org/t/conditional-conversion-tricks/577)

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**Author:** [@mfreitas](https://discourse.myhdl.org/u/mfreitas)\
**Replies:** 3\
**Last updated:** [July 14, 2025, 12:13pm UTC](https://discourse.myhdl.org/t/conditional-conversion-tricks/577 "2025-07-14T12:13:11Z")

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Hi! I have some use cases where I do customization on instantiated objects by changing a default parameter and then I get parts of the code disabled inside “if” blocks. So far this has worked fine because converted “if F…

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## [Converting enum code (integer) to EnumItem](https://discourse.myhdl.org/t/converting-enum-code-integer-to-enumitem/574)

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**Author:** [@mfreitas](https://discourse.myhdl.org/u/mfreitas)\
**Replies:** 9\
**Last updated:** [April 15, 2025, 8:39pm UTC](https://discourse.myhdl.org/t/converting-enum-code-integer-to-enumitem/574 "2025-04-15T20:39:06Z")

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Hi guys, I have been working with MyHDL for a few months and I find it really great. Thanks for bringing joy of hardware programing back :wink: Today I’ve revisited an issue I gave up in the past and I still can’t conv…

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## [New to MyHDL - how should I connect outputs to inputs properly?](https://discourse.myhdl.org/t/new-to-myhdl-how-should-i-connect-outputs-to-inputs-properly/571)

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**Author:** [@drtitus](https://discourse.myhdl.org/u/drtitus)\
**Replies:** 3\
**Last updated:** [January 24, 2025, 12:33pm UTC](https://discourse.myhdl.org/t/new-to-myhdl-how-should-i-connect-outputs-to-inputs-properly/571 "2025-01-24T12:33:41Z")

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I’m doing something wrong here - as a bit of a background, I’m a long-time software developer (boo, hiss! I get it) trying to get my head around MyHDL and Verilog for digital design, and in principle I think I understand…

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## [Cosimulation output port conflict (X)](https://discourse.myhdl.org/t/cosimulation-output-port-conflict-x/569)

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**Author:** [@vpascucci](https://discourse.myhdl.org/u/vpascucci)\
**Replies:** 2\
**Last updated:** [October 4, 2024, 7:51am UTC](https://discourse.myhdl.org/t/cosimulation-output-port-conflict-x/569 "2024-10-04T07:51:07Z")

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Hello, I have a very simple blink module as follows: @block def Blink(clk:SignalType, rst:ResetSignal, blink, enable, period): count = Signal(modbv(0)\[20:\]) @always(clk.posedge) def logic(): if enable: if cou…

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## [Cosimulation with waveform dump](https://discourse.myhdl.org/t/cosimulation-with-waveform-dump/185)

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**Author:** [@ycgeng](https://discourse.myhdl.org/u/ycgeng)\
**Replies:** 2\
**Last updated:** [October 1, 2024, 9:35pm UTC](https://discourse.myhdl.org/t/cosimulation-with-waveform-dump/185 "2024-10-01T21:35:07Z")

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Hi, I am trying to Cosimulate my Fifo design. It always report an error like AttributeError: 'Cosimulation' object has no attribute 'name' When checking and trying various solution, I found that it is related to th…

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## [Managing scattered codebase](https://discourse.myhdl.org/t/managing-scattered-codebase/568)

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**Author:** [@vpascucci](https://discourse.myhdl.org/u/vpascucci)\
**Replies:** 0\
**Last updated:** [September 30, 2024, 4:12pm UTC](https://discourse.myhdl.org/t/managing-scattered-codebase/568 "2024-09-30T16:12:25Z")

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Hello, I am trying to figure out a lean workflow with myhdl. My first instinct is to try and replicate my VHDL workflow. There I have my codebase scattered around several repositories, which are then included as needed …

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## [VHDL constant value overflow](https://discourse.myhdl.org/t/vhdl-constant-value-overflow/326)

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**Author:** [@mhavu](https://discourse.myhdl.org/u/mhavu)\
**Replies:** 16\
**Last updated:** [July 24, 2024, 10:35am UTC](https://discourse.myhdl.org/t/vhdl-constant-value-overflow/326 "2024-07-24T10:35:02Z")

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How do MyHDL people usually work around the VHDL size limit for integer literals? Consider the following MyHDL code: Y\_LEN = 71 Y\_MIN, Y\_MAX = (-2\*\*(Y\_LEN - 1), 2\*\*(Y\_LEN - 1)) y = Signal(intbv(0, Y\_MIN, Y\_MAX)) # An a…

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## [AttributeError: 'List' object has no attribute 'vhd'...I m getting this error while i want to make a circuit that does the convolution of square wave and triangular wave ...Please suggest me any modifications in this code so that i will get the desired op](https://discourse.myhdl.org/t/attributeerror-list-object-has-no-attribute-vhd-i-m-getting-this-error-while-i-want-to-make-a-circuit-that-does-the-convolution-of-square-wave-and-triangular-wave-please-suggest-me-any-modifications-in-this-code-so-that-i-will-get-the-desired-op/565)

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**Author:** [@muzaim11](https://discourse.myhdl.org/u/muzaim11)\
**Replies:** 2\
**Last updated:** [March 18, 2024, 10:09am UTC](https://discourse.myhdl.org/t/attributeerror-list-object-has-no-attribute-vhd-i-m-getting-this-error-while-i-want-to-make-a-circuit-that-does-the-convolution-of-square-wave-and-triangular-wave-please-suggest-me-any-modifications-in-this-code-so-that-i-will-get-the-desired-op/565 "2024-03-18T10:09:11Z")

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from myhdl import \* import matplotlib.pyplot as plt from mmm import sig\_square,sig\_triag @block def sin\_1( sel,out): sig1=tuple(\[(sig\_square(x//100)) for x in range(1000)\]) sig2=tuple(\[(sig\_triag(x//100)) for x …

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## [MyHDL project explorer](https://discourse.myhdl.org/t/myhdl-project-explorer/561)

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**Author:** [@devbisme](https://discourse.myhdl.org/u/devbisme)\
**Replies:** 4\
**Last updated:** [September 8, 2023, 9:20pm UTC](https://discourse.myhdl.org/t/myhdl-project-explorer/561 "2023-09-08T21:20:10Z")

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I built a single-page web app (RepoRecon) that displays filterable, searchable, sortable tables of Github repositories that pertain to certain topics. One of the topics I selected is MyHDL.

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## [How to use cosimulation on a windows machine?](https://discourse.myhdl.org/t/how-to-use-cosimulation-on-a-windows-machine/552)

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**Author:** [@stekar](https://discourse.myhdl.org/u/stekar)\
**Replies:** 5\
**Last updated:** [April 10, 2023, 1:53pm UTC](https://discourse.myhdl.org/t/how-to-use-cosimulation-on-a-windows-machine/552 "2023-04-10T13:53:51Z")

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Just tried the myhdl.vpi on my Windows machine. Did’nt get it to work. First i used the following statement to run cosimulation: return Cosimulation(“vvp -m ./myhdl.vpi unit\_control.o”, CLKIN=CLKIN,RESET\_N=RESET\_N, FAU…

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## [How to get the latest Version of myhdl 2](https://discourse.myhdl.org/t/how-to-get-the-latest-version-of-myhdl-2/555)

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**Author:** [@stekar](https://discourse.myhdl.org/u/stekar)\
**Replies:** 4\
**Last updated:** [February 26, 2023, 6:27pm UTC](https://discourse.myhdl.org/t/how-to-get-the-latest-version-of-myhdl-2/555 "2023-02-26T18:27:02Z")

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I followed the tip in ‘How to get the latest Version of myhdl’ but it seems i did not succeed. (I renew the topic here) I uninstalled myhdl first. then i did as proposed (in a virtual environment called installation): …

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## [How to get latest version of myhdl?](https://discourse.myhdl.org/t/how-to-get-latest-version-of-myhdl/551)

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**Author:** [@noam](https://discourse.myhdl.org/u/noam)\
**Replies:** 12\
**Last updated:** [December 11, 2022, 7:29am UTC](https://discourse.myhdl.org/t/how-to-get-latest-version-of-myhdl/551 "2022-12-11T07:29:38Z")

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Hi, I was following the official MyHDL site instructions, and installed myhdl using “pip install myhdl” and “pip install --upgrade myhdl”. As a result, I got version 0.11 which dates back to 2019 and does not work wi…

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## [Pull Request Cleanup](https://discourse.myhdl.org/t/pull-request-cleanup/554)

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**Author:** [@davekeeshan](https://discourse.myhdl.org/u/davekeeshan)\
**Replies:** 1\
**Last updated:** [December 8, 2022, 2:25pm UTC](https://discourse.myhdl.org/t/pull-request-cleanup/554 "2022-12-08T14:25:02Z")

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I have been doing some work behind the scenes to get myhdl working with github actions. So far it is looking great and working. I am thinking of adding code coverage next. I have mentioned to @josy that I would love to…

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## [Initialisation behaviour can be problematic](https://discourse.myhdl.org/t/initialisation-behaviour-can-be-problematic/549)

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**Author:** [@stekar](https://discourse.myhdl.org/u/stekar)\
**Replies:** 6\
**Last updated:** [November 19, 2022, 8:43pm UTC](https://discourse.myhdl.org/t/initialisation-behaviour-can-be-problematic/549 "2022-11-19T20:43:36Z")

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After my conclusion ‘best practice’ i just came upon another behavior which differs between myhdl and cosim when producing synthesizable code: The initialization of variables (moreover ‘adding to a variable doesn’t w…

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## [Best practice: my conclusion after months of development](https://discourse.myhdl.org/t/best-practice-my-conclusion-after-months-of-development/548)

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**Author:** [@stekar](https://discourse.myhdl.org/u/stekar)\
**Replies:** 2\
**Last updated:** [November 12, 2022, 8:25pm UTC](https://discourse.myhdl.org/t/best-practice-my-conclusion-after-months-of-development/548 "2022-11-12T20:25:17Z")

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Please comment my conclusion, even after months of development with myhdl i have not seen all of course. my conclusion on pure python simulation and cosim is essentially that you have to do both all the time while devel…

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## [myhdl.AlwaysCombError: sensitivity list is empty](https://discourse.myhdl.org/t/myhdl-alwayscomberror-sensitivity-list-is-empty/547)

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**Author:** [@MohitKumar](https://discourse.myhdl.org/u/MohitKumar)\
**Replies:** 1\
**Last updated:** [November 9, 2022, 9:41am UTC](https://discourse.myhdl.org/t/myhdl-alwayscomberror-sensitivity-list-is-empty/547 "2022-11-09T09:41:38Z")

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Hi everyone, I am trying to develop a 8\*8 bit Wallace tree multiplier in MyHDL. I have written the code for the same however I am facing this error myhdl.AlwaysCombError: sensitivity list is empty when I am trying to …

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## [Sub module Verilog synthesis error](https://discourse.myhdl.org/t/sub-module-verilog-synthesis-error/544)

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**Author:** [@steveg](https://discourse.myhdl.org/u/steveg)\
**Replies:** 3\
**Last updated:** [June 17, 2022, 4:28pm UTC](https://discourse.myhdl.org/t/sub-module-verilog-synthesis-error/544 "2022-06-17T16:28:10Z")

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Hi All, I have an exmaple of code that produces output VHDL that is correct and Verilog that is incorrect. The incorrectness in Verilog stems from the fact there is an assignment to a wire type that should be a reg typ…

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## [Sign extend bits](https://discourse.myhdl.org/t/sign-extend-bits/542)

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**Author:** [@steveg](https://discourse.myhdl.org/u/steveg)\
**Replies:** 2\
**Last updated:** [May 10, 2022, 10:11pm UTC](https://discourse.myhdl.org/t/sign-extend-bits/542 "2022-05-10T22:11:59Z")

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Hi All, I have a 4 bit number that I need to sign extend to say ‘WIDTH’ bits … I have read online some older banter but not sure out of that how to do this or if it is supported easily? I can of course use an if then t…

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## [Multiple @always\_comb needed - why?](https://discourse.myhdl.org/t/multiple-always-comb-needed-why/535)

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**Author:** [@steveg](https://discourse.myhdl.org/u/steveg)\
**Replies:** 35\
**Last updated:** [April 26, 2022, 8:38pm UTC](https://discourse.myhdl.org/t/multiple-always-comb-needed-why/535 "2022-04-26T20:38:54Z")

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Hi All, I think I am missing something on how I an constructing combinatorial logic, as it seems like I need to specify a separate comb process if I calc and then use this calc further on in the same process. (I hope …

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## [Signed error with lshift](https://discourse.myhdl.org/t/signed-error-with-lshift/539)

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**Author:** [@steveg](https://discourse.myhdl.org/u/steveg)\
**Replies:** 3\
**Last updated:** [April 24, 2022, 8:50pm UTC](https://discourse.myhdl.org/t/signed-error-with-lshift/539 "2022-04-24T20:50:44Z")

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Hi All, I want to shift a signal left if the msbit is false in a clocked process… (Verilog has no issue with this) shift.next = mult \<\< ~mult\[WIDTH2M-1\] i.e. of mult\[WIDTH2M-1\] is false, shift left otherwise do not. T…

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## [ToVerilogWarning: Output port is read internally:](https://discourse.myhdl.org/t/toverilogwarning-output-port-is-read-internally/534)

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**Author:** [@steveg](https://discourse.myhdl.org/u/steveg)\
**Replies:** 6\
**Last updated:** [April 23, 2022, 5:41am UTC](https://discourse.myhdl.org/t/toverilogwarning-output-port-is-read-internally/534 "2022-04-23T05:41:53Z")

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Hi, I find I get benign warning for using my output of my block internally - this looks like a redundant message and should be removed? Its always nice to compile and not get any warnings / errors. Regards, Steve.

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## [Sanity check: Ps/2 Keyboard on an fpga](https://discourse.myhdl.org/t/sanity-check-ps-2-keyboard-on-an-fpga/531)

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**Author:** [@BlueMagma](https://discourse.myhdl.org/u/BlueMagma)\
**Replies:** 2\
**Last updated:** [April 21, 2022, 1:31am UTC](https://discourse.myhdl.org/t/sanity-check-ps-2-keyboard-on-an-fpga/531 "2022-04-21T01:31:54Z")

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Hi, I’m in need of some sanity check on my myHDL code. I’ve written a PS/2 interface with the intent on emulating a Keyboard on an FPGA. Bare in mind I am a novice in HDL and FPGA, playing around as a hobby. My testbe…

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## [Preserve hierarchy](https://discourse.myhdl.org/t/preserve-hierarchy/379)

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**Author:** [@krs](https://discourse.myhdl.org/u/krs)\
**Replies:** 8\
**Last updated:** [April 19, 2022, 11:17am UTC](https://discourse.myhdl.org/t/preserve-hierarchy/379 "2022-04-19T11:17:36Z")

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Hello, I see that for all the myhdl sub modules that during conversion, the hierarchy is flattened. Is there an easy solution to preserve hierarchies ? Is this feature available now ? Thank you

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## [MyHDL synthesis support / jupyosys](https://discourse.myhdl.org/t/myhdl-synthesis-support-jupyosys/431)

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**Author:** [@hackfin](https://discourse.myhdl.org/u/hackfin)\
**Replies:** 1\
**Last updated:** [January 26, 2022, 2:21pm UTC](https://discourse.myhdl.org/t/myhdl-synthesis-support-jupyosys/431 "2022-01-26T14:21:12Z")

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Hi there, I’ve been integrating a so far experimental yosys backend into MyHDL that directly creates synthesizeable module hierarchies without the transfer through V\* languages. It’s now at a stage where you can get si…

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## [Trying to create a fifo through a queue](https://discourse.myhdl.org/t/trying-to-create-a-fifo-through-a-queue/491)

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**Author:** [@Albert](https://discourse.myhdl.org/u/Albert)\
**Replies:** 7\
**Last updated:** [January 20, 2022, 7:05am UTC](https://discourse.myhdl.org/t/trying-to-create-a-fifo-through-a-queue/491 "2022-01-20T07:05:54Z")

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I am trying to create a fifo by a queue (this is also mentioned in the MyHDL manual) but get errors when I try to convert it to VHDL. Not sure if this are MyHDL errors or normal Python errors. convert\_model.py ’ from …

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## [How to do cosimulation with a commercial tool?](https://discourse.myhdl.org/t/how-to-do-cosimulation-with-a-commercial-tool/490)

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**Author:** [@bitdiver](https://discourse.myhdl.org/u/bitdiver)\
**Replies:** 3\
**Last updated:** [January 11, 2022, 9:20pm UTC](https://discourse.myhdl.org/t/how-to-do-cosimulation-with-a-commercial-tool/490 "2022-01-11T21:20:42Z")

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Hello, there is a howto available to run a cosimulation between MyHDL and verilog on Windows here: Co-simulation with Verilog — MyHDL 0.11 documentation However, I was wondering what steps I need to take to setup cosim…

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## [Creating a group of Signals](https://discourse.myhdl.org/t/creating-a-group-of-signals/487)

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**Author:** [@Mark](https://discourse.myhdl.org/u/Mark)\
**Replies:** 5\
**Last updated:** [January 4, 2022, 11:12am UTC](https://discourse.myhdl.org/t/creating-a-group-of-signals/487 "2022-01-04T11:12:48Z")

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Is there a recommended MyHDL way to create a group of Signals? In Python, I can declare a bunch of empty lists as: a,b,c = \[\],\[\],\[\] or a,b,c = \[0\]\*16,\[0\]\*8,\[0,1,2\] Is there a more concise way in Python to declare a …

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## [MyHDL Signals inside functions not showing up in VCD](https://discourse.myhdl.org/t/myhdl-signals-inside-functions-not-showing-up-in-vcd/488)

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**Author:** [@Mark](https://discourse.myhdl.org/u/Mark)\
**Replies:** 1\
**Last updated:** [January 2, 2022, 3:59pm UTC](https://discourse.myhdl.org/t/myhdl-signals-inside-functions-not-showing-up-in-vcd/488 "2022-01-02T15:59:37Z")

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Should I be able to see these in the generated VCD file? @always(clk.posedge) def MentorCluster(): mentorq0, mentorq1, mentorq2, mentorq3 = \[\[Signal(0) for j in range(10)\] for i in range(4)\] I can see al…

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## [Initial block in MyHDL](https://discourse.myhdl.org/t/initial-block-in-myhdl/486)

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**Author:** [@Mark](https://discourse.myhdl.org/u/Mark)\
**Replies:** 2\
**Last updated:** [January 1, 2022, 7:49pm UTC](https://discourse.myhdl.org/t/initial-block-in-myhdl/486 "2022-01-01T19:49:23Z")

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Is there a recommended way to create an initial block in MyHDL? I found a Stack Overflow article on how to infer one into Verilog, but not how to do something like: #20 x = 0; #20 x = 1; to hack stimulus, etc. C…

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