# Latest

**URL:** https://discourse.myhdl.org/latest.md?page=2

[Latest](https://discourse.myhdl.org/latest.md) · [Categories](https://discourse.myhdl.org/categories.md)

**Page:** 3

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## [Is implementing a classification algorithm possible w/ MyHDL?](https://discourse.myhdl.org/t/is-implementing-a-classification-algorithm-possible-w-myhdl/421)

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**Author:** [@akwan](https://discourse.myhdl.org/u/akwan)\
**Replies:** 1\
**Last updated:** [March 25, 2020, 11:59am UTC](https://discourse.myhdl.org/t/is-implementing-a-classification-algorithm-possible-w-myhdl/421 "2020-03-25T11:59:44Z")

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Hello, I am trying to implement a OneR algorithm with MyHDL. Is it possible to model this with myhdl or would I have to make modifications/adjustments in order for it to convert successfully? An example of a OneR impleme…

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## [How to do signed operations on intbv](https://discourse.myhdl.org/t/how-to-do-signed-operations-on-intbv/419)

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**Author:** [@saudalwasly](https://discourse.myhdl.org/u/saudalwasly)\
**Replies:** 3\
**Last updated:** [March 18, 2020, 4:44pm UTC](https://discourse.myhdl.org/t/how-to-do-signed-operations-on-intbv/419 "2020-03-18T16:44:18Z")

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I am trying to implement a simple ALU with add and subtract operations. I got an error once the resulted value is less than 0! Can anyone provide me with an example of how to do it correctly in MyHDL? Thank you in adva…

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## [How can I implement this?](https://discourse.myhdl.org/t/how-can-i-implement-this/416)

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**Author:** [@krs](https://discourse.myhdl.org/u/krs)\
**Replies:** 2\
**Last updated:** [March 3, 2020, 8:57pm UTC](https://discourse.myhdl.org/t/how-can-i-implement-this/416 "2020-03-03T20:57:07Z")

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Hello I would like to implement the following logic with a for loop in myhdl. Can anyone tell me how to do it ? Thanks intMux = \[Signal(intbv(0)\[16:\]) for i in range(8)\] @always(reset.posedge, clk.posedge) def statsGen…

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## [I need counter 4-bit please help me](https://discourse.myhdl.org/t/i-need-counter-4-bit-please-help-me/413)

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**Author:** [@reza.ahadi](https://discourse.myhdl.org/u/reza.ahadi)\
**Replies:** 7\
**Last updated:** [February 17, 2020, 9:22am UTC](https://discourse.myhdl.org/t/i-need-counter-4-bit-please-help-me/413 "2020-02-17T09:22:19Z")

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hi I need counter 4-bit with up count and down count in myhdl and convert to verilog or vhdl. please help me

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## [Design a 8-bit counter to myhdl and convert to vhdl](https://discourse.myhdl.org/t/design-a-8-bit-counter-to-myhdl-and-convert-to-vhdl/411)

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**Author:** [@reza.ahadi](https://discourse.myhdl.org/u/reza.ahadi)\
**Replies:** 1\
**Last updated:** [February 12, 2020, 8:05am UTC](https://discourse.myhdl.org/t/design-a-8-bit-counter-to-myhdl-and-convert-to-vhdl/411 "2020-02-12T08:05:39Z")

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hi my friends.can your design a 8-bit counter into myhdl and convert to vhdl? please a send me designing file

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## [Allow kwargs in module interfaces](https://discourse.myhdl.org/t/allow-kwargs-in-module-interfaces/404)

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**Author:** [@jvillar](https://discourse.myhdl.org/u/jvillar)\
**Replies:** 3\
**Last updated:** [January 21, 2020, 1:22pm UTC](https://discourse.myhdl.org/t/allow-kwargs-in-module-interfaces/404 "2020-01-21T13:22:52Z")

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Hi! There are use cases where not all members of an interface are known at coding time, let’s think about a highly parameterizable component that can modify it’s interface depending on the value of certain parameters, s…

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## [Simplified signal naming when possible](https://discourse.myhdl.org/t/simplified-signal-naming-when-possible/403)

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**Author:** [@jvillar](https://discourse.myhdl.org/u/jvillar)\
**Replies:** 6\
**Last updated:** [January 20, 2020, 6:19pm UTC](https://discourse.myhdl.org/t/simplified-signal-naming-when-possible/403 "2020-01-20T18:19:04Z")

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Hi! Since the introduction of the block decorator, all functions in the calltrace of a design, have to be decorated by it. This way, all these functions make a contribution to the name of its internal signals. This beha…

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## [MyHDL Resources](https://discourse.myhdl.org/t/myhdl-resources/407)

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**Author:** [@devbisme](https://discourse.myhdl.org/u/devbisme)\
**Replies:** 7\
**Last updated:** [January 5, 2020, 2:10pm UTC](https://discourse.myhdl.org/t/myhdl-resources/407 "2020-01-05T14:10:05Z")

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I’ve updated the MyHDL Resources page with whatever new projects I could find on Github. If anyone has any new MyHDL-related tutorials/projects/tools, please add them to the page and issue a PR. Thanks!

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## [Cannot open some .vcd files in "Scansion" waveform viewer](https://discourse.myhdl.org/t/cannot-open-some-vcd-files-in-scansion-waveform-viewer/401)

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**Author:** [@Susantha\_Wijesinghe](https://discourse.myhdl.org/u/Susantha_Wijesinghe)\
**Replies:** 1\
**Last updated:** [October 27, 2019, 3:13pm UTC](https://discourse.myhdl.org/t/cannot-open-some-vcd-files-in-scansion-waveform-viewer/401 "2019-10-27T15:13:19Z")

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Some myHDL created .vcd file cannot be opened by Scansion waveform viewer, giving an error message . However, the same .vcd file can be opened in gtkWave without any problem. I noticed that some .vcd files created by myH…

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## [Another MyHDL VHDL conversion bug](https://discourse.myhdl.org/t/another-myhdl-vhdl-conversion-bug/393)

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**Author:** [@ThomasHornschuh](https://discourse.myhdl.org/u/ThomasHornschuh)\
**Replies:** 13\
**Last updated:** [October 17, 2019, 12:15am UTC](https://discourse.myhdl.org/t/another-myhdl-vhdl-conversion-bug/393 "2019-10-17T00:15:54Z")

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The following line self.res\_o.next = concat( modbv(0)\[31:\], self.op1\_i \< self.op2\_i ) is converted to this VHDL code: self\_res\_o\_num \<= unsigned'(unsigned'("0000000000000000000000000000000") & (self\_op1\_i\_num \< self\_…

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## [Mutiple traces/simulations in one run](https://discourse.myhdl.org/t/mutiple-traces-simulations-in-one-run/398)

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**Author:** [@ThomasHornschuh](https://discourse.myhdl.org/u/ThomasHornschuh)\
**Replies:** 4\
**Last updated:** [October 13, 2019, 11:21am UTC](https://discourse.myhdl.org/t/mutiple-traces-simulations-in-one-run/398 "2019-10-13T11:21:35Z")

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I want to run several simulations (e.g for different instances or the same instance with different parameters) from one main script. So I have a function: def test(inst,\*\*kwagrs): inst.config\_sim(\*\*kwagrs) inst…

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## [How can I use lists of signals and still convert to verilog](https://discourse.myhdl.org/t/how-can-i-use-lists-of-signals-and-still-convert-to-verilog/396)

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**Author:** [@etch32](https://discourse.myhdl.org/u/etch32)\
**Replies:** 12\
**Last updated:** [September 18, 2019, 1:21pm UTC](https://discourse.myhdl.org/t/how-can-i-use-lists-of-signals-and-still-convert-to-verilog/396 "2019-09-18T13:21:15Z")

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Hello, new myhdl user here. I’ve hit my first hurdle that I haven’t been able to solve perusing the many excellent examples out there. In fact, I’ve seen others with similar problem but haven’t seen a resolution. I initi…

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## [Programming Altera serial configuration device with Python](https://discourse.myhdl.org/t/programming-altera-serial-configuration-device-with-python/394)

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**Author:** [@kc64](https://discourse.myhdl.org/u/kc64)\
**Replies:** 13\
**Last updated:** [September 12, 2019, 11:37am UTC](https://discourse.myhdl.org/t/programming-altera-serial-configuration-device-with-python/394 "2019-09-12T11:37:07Z")

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We’ve been programming a Cyclone 10 device using Quartus Prime and a USB blaster. Now, I would like to replace the USB blaster with an FTDI FT2232H device in MPSSE mode and bit bang the interface with a Python script tha…

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## [Conversion problem with shadow signal](https://discourse.myhdl.org/t/conversion-problem-with-shadow-signal/391)

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**Author:** [@ThomasHornschuh](https://discourse.myhdl.org/u/ThomasHornschuh)\
**Replies:** 8\
**Last updated:** [September 3, 2019, 7:27am UTC](https://discourse.myhdl.org/t/conversion-problem-with-shadow-signal/391 "2019-09-03T07:27:34Z")

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Hi, I have noticed that the use of shadow signals lead often to conversion problems. I have not found the exact conditions yet, so I have no small reproducible example. But in my github repo https://github.com/bonfirep…

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## [Unexpected signal name in converted VHDL](https://discourse.myhdl.org/t/unexpected-signal-name-in-converted-vhdl/389)

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**Author:** [@ThomasHornschuh](https://discourse.myhdl.org/u/ThomasHornschuh)\
**Replies:** 4\
**Last updated:** [August 1, 2019, 5:47pm UTC](https://discourse.myhdl.org/t/unexpected-signal-name-in-converted-vhdl/389 "2019-08-01T17:47:04Z")

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Hi, when converting my Design to VHDL I get unexpected results. I have defined an interface: # Wishbone Bus interface bundle from myhdl import \* class Wishbone\_bundle: def \_\_init\_\_(self,master,adrHigh,adrLow,data…

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## [How to dynamically infer ports?](https://discourse.myhdl.org/t/how-to-dynamically-infer-ports/387)

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**Author:** [@ThomasHornschuh](https://discourse.myhdl.org/u/ThomasHornschuh)\
**Replies:** 6\
**Last updated:** [August 1, 2019, 2:34pm UTC](https://discourse.myhdl.org/t/how-to-dynamically-infer-ports/387 "2019-08-01T14:34:51Z")

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I have just started with MyHDL and was able to build a demo ip core with it. https://github.com/bonfireprocessor/bonfire-pwm The project is a simple PWM driver for RGB LEDs with a Wishbone interface. The only thing I’m…

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## [Vcd hierarchy naming](https://discourse.myhdl.org/t/vcd-hierarchy-naming/359)

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**Author:** [@paulM](https://discourse.myhdl.org/u/paulM)\
**Replies:** 13\
**Last updated:** [June 28, 2019, 3:53pm UTC](https://discourse.myhdl.org/t/vcd-hierarchy-naming/359 "2019-06-28T15:53:17Z")

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Hi, At IMEC we use myhdl extensively for system exploration and design. Recently we migrated all our projects to the newest (github) version, and rewote the designs to use the block-decorator. Unfortunately this has a s…

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## [Python 3.7 support / new release](https://discourse.myhdl.org/t/python-3-7-support-new-release/376)

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**Author:** [@chipmuenk](https://discourse.myhdl.org/u/chipmuenk)\
**Replies:** 5\
**Last updated:** [May 31, 2019, 10:45pm UTC](https://discourse.myhdl.org/t/python-3-7-support-new-release/376 "2019-05-31T22:45:32Z")

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As far as I understand, PR #267 and #264 fix the Python 3.7 incompatibility due to the “async” keyword. Would it be possible to do a bugfix release on PyPI including these PR’s? I have just started to integrate myHDL in…

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## [Problem of async](https://discourse.myhdl.org/t/problem-of-async/382)

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**Author:** [@azmos](https://discourse.myhdl.org/u/azmos)\
**Replies:** 6\
**Last updated:** [May 16, 2019, 6:30pm UTC](https://discourse.myhdl.org/t/problem-of-async/382 "2019-05-16T18:30:35Z")

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Hello, I am new user of MyHDL but I faced the problem of async which is now a keyword of Python 3.7 but before Python 3.5 was just a global variable. Is there any trick to overpass this problem? Thanks.

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## [Large memory consumption](https://discourse.myhdl.org/t/large-memory-consumption/377)

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**Author:** [@kranerup](https://discourse.myhdl.org/u/kranerup)\
**Replies:** 13\
**Last updated:** [May 14, 2019, 7:27am UTC](https://discourse.myhdl.org/t/large-memory-consumption/377 "2019-05-14T07:27:53Z")

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We have very large MyHDL designs and are in the process of migrating from MyHDL 0.8 to 0.10. Unfortunately some of our designs runs out of memory (\> 128Gbyte) when generating Verilog. It seems there is at least a factor…

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## [Vendor specific instance simulation](https://discourse.myhdl.org/t/vendor-specific-instance-simulation/380)

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**Author:** [@krs](https://discourse.myhdl.org/u/krs)\
**Replies:** 1\
**Last updated:** [April 19, 2019, 9:56am UTC](https://discourse.myhdl.org/t/vendor-specific-instance-simulation/380 "2019-04-19T09:56:05Z")

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How does people here do vendor specific instance simulation ? Can FIFO memory etc designed in myhdl while converting to verilog/vhdl create vendor specific instance blocks? How do people who use myhdl use a FIFO for si…

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## [Conversion naming issue](https://discourse.myhdl.org/t/conversion-naming-issue/373)

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**Author:** [@krs](https://discourse.myhdl.org/u/krs)\
**Replies:** 8\
**Last updated:** [April 5, 2019, 3:20pm UTC](https://discourse.myhdl.org/t/conversion-naming-issue/373 "2019-04-05T15:20:22Z")

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In the following code: def block\_connect(self, pars, reset, clk, pipe\_inpA, pipe\_inpB, pipe\_out\_activ): ... \< some code\> ... ... @always\_comb def shiftOperand\_signal…

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## [Verilog conversion to write results to a file?](https://discourse.myhdl.org/t/verilog-conversion-to-write-results-to-a-file/372)

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**Author:** [@Dani](https://discourse.myhdl.org/u/Dani)\
**Replies:** 12\
**Last updated:** [April 4, 2019, 12:24pm UTC](https://discourse.myhdl.org/t/verilog-conversion-to-write-results-to-a-file/372 "2019-04-04T12:24:47Z")

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Dear All, Is there an easy way to insert a macro inside the myhdl code to generate a verilog conversion to generate data logs to a file. Like: Myhdl Verilog f = ope…

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## [Monitoring Signal variable outside a class realtime](https://discourse.myhdl.org/t/monitoring-signal-variable-outside-a-class-realtime/371)

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**Author:** [@krs](https://discourse.myhdl.org/u/krs)\
**Replies:** 4\
**Last updated:** [April 1, 2019, 11:33am UTC](https://discourse.myhdl.org/t/monitoring-signal-variable-outside-a-class-realtime/371 "2019-04-01T11:33:59Z")

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Hello, Lets say i have a class with a method: class TestBlk(): def block\_connect(self, reset, clk, stimulus): test=Signal(bool(1)) My testbench needs to monitor the signal changes of the variable test from out…

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## [Don't care / unknown](https://discourse.myhdl.org/t/dont-care-unknown/368)

<div class="topic-metadata">

**Author:** [@philn16](https://discourse.myhdl.org/u/philn16)\
**Replies:** 4\
**Last updated:** [March 28, 2019, 11:15pm UTC](https://discourse.myhdl.org/t/dont-care-unknown/368 "2019-03-28T23:15:17Z")

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Is there a way of assigning a variable a don’t care / unknown type in MyHDL? For example, in verilog I’d write wire \[3:0\]dontcare=4’bxxxx;

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## [Open Source Resource Estimator Tool](https://discourse.myhdl.org/t/open-source-resource-estimator-tool/367)

<div class="topic-metadata">

**Author:** [@krs](https://discourse.myhdl.org/u/krs)\
**Replies:** 2\
**Last updated:** [March 26, 2019, 8:17am UTC](https://discourse.myhdl.org/t/open-source-resource-estimator-tool/367 "2019-03-26T08:17:53Z")

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Hello are there some free/open source tools with which I could get a rough estimate of resource usage from my myhdl code ? Alternately are there any opensource tools to estimate it from my converted design to Verilog/VHD…

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## [Testbenches in myhdl or cocotb](https://discourse.myhdl.org/t/testbenches-in-myhdl-or-cocotb/369)

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**Author:** [@krs](https://discourse.myhdl.org/u/krs)\
**Replies:** 1\
**Last updated:** [March 23, 2019, 9:26pm UTC](https://discourse.myhdl.org/t/testbenches-in-myhdl-or-cocotb/369 "2019-03-23T21:26:21Z")

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Hello, Are there really any benefits of using cocotb for simulation when one use myhdl for coding ? I guess I could do unit tests in python myhdl for simulation (did not try it though). Cocotb also provides an easy fr…

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## [Function not converting, but deflated code does](https://discourse.myhdl.org/t/function-not-converting-but-deflated-code-does/365)

<div class="topic-metadata">

**Author:** [@Dani](https://discourse.myhdl.org/u/Dani)\
**Replies:** 8\
**Last updated:** [March 23, 2019, 10:59am UTC](https://discourse.myhdl.org/t/function-not-converting-but-deflated-code-does/365 "2019-03-23T10:59:49Z")

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Dear All, Well I try something that is simplistic, but I have a low mileage on Myhdl. If one of the senior here around could have a look and explain the beginner where he is mistaken he would be very thankful :slight\_sm…

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## [How to simulate for the ROM type design](https://discourse.myhdl.org/t/how-to-simulate-for-the-rom-type-design/362)

<div class="topic-metadata">

**Author:** [@wisdomz](https://discourse.myhdl.org/u/wisdomz)\
**Replies:** 17\
**Last updated:** [March 12, 2019, 2:18pm UTC](https://discourse.myhdl.org/t/how-to-simulate-for-the-rom-type-design/362 "2019-03-12T14:18:52Z")

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It is my myhdl case, I want to use Python generate some data pattern , then put it into ROM from myhdl import Signal, ResetSignal, modbv,intbv from myhdl import block, always\_seq, Signal, modbv ,always\_comb from myhdl …

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## ['tuple' object has no attribute 'config\_sim'](https://discourse.myhdl.org/t/tuple-object-has-no-attribute-config-sim/361)

<div class="topic-metadata">

**Author:** [@wisdomz](https://discourse.myhdl.org/u/wisdomz)\
**Replies:** 1\
**Last updated:** [February 25, 2019, 10:08am UTC](https://discourse.myhdl.org/t/tuple-object-has-no-attribute-config-sim/361 "2019-02-25T10:08:14Z")

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I get the following fir example design from open source from myhdl import \* #=\[10,11,13,154\] def m\_firfilt(clock, reset, sig\_in, sig\_out, coef): “”" “”" taps = \[Signal(intbv(0, min=sig\_in.min, max=sig\_in.max)) for …

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