# Add new Bool type to MyHDL?

**URL:** <https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281>\
**Category:** Enhancement Request\
**Created:** [July 3, 2018, 2:49pm UTC](https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281 "2018-07-03T14:49:09Z")\
**Posts on this page:** 10\
**Page:** 1

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [July 3, 2018, 2:49pm UTC](https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281/1 "2018-07-03T14:49:09Z")

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Hi,

While designing modules using bool signals asserted high and others asserted low, I thought it could be a good idea to create a new `Bool()` type where the polarity is internally managed. Like with `ResetSignal()`.

For example, using the Flexbus (parallel bus) of a microcontroller, there is ALE (Address Latch Enable) which is asserted high and CS and OE that are asserted low.

These signals could be instantiated like this :

```python
ale = Signal(Bool(init_value=False, asserted_high=True))
cs = Signal(Bool(init_value=False, asserted_high=False))
oe = Signal(Bool(init_value=False, asserted_high=False))

```

Testing would be :

```python
    if ale :
        # do something
    if cs :
        # do something else

```

Asserting would be :

```python
    ale.next = True
    cs.next = True

```

De-asserting would be :

```python
    ale.next = False
    cs.next = False

```

What do you think of this proposition ?

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<div class="post-metadata">

**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [July 4, 2018, 11:16am UTC](https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281/2 "2018-07-04T11:16:28Z")

</div>

I don’t think we need this.  
And I am sure I wouldn’t use it. I treat all internal signals active high and if necessary change the polarity at the top level. Most of the time, it doesn’t always hold …

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<div class="post-metadata">

**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [July 4, 2018, 5:22pm UTC](https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281/3 "2018-07-04T17:22:35Z")

</div>

Adding an inverter adds one level of logic which modifies the timings. Most often, this is not a problem. Most often…

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<div class="post-metadata">

**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [July 4, 2018, 5:41pm UTC](https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281/4 "2018-07-04T17:41:11Z")

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The vendor tool will take care of that. It will optimize that inverter into the input or output block or into the next register.

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<div class="post-metadata">

**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [July 4, 2018, 5:57pm UTC](https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281/5 "2018-07-04T17:57:21Z")

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Yes. Most often…

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<div class="post-metadata">

**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [July 4, 2018, 6:26pm UTC](https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281/6 "2018-07-04T18:26:07Z")

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99.9 % will do? IMO asynchronous buses like you describe should not suffer from that 1 extra level of logic, if ever this is not optimized away. Wait, the Flexbus is actually synchronous, however the above still applies.

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<div class="post-metadata">

**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [July 4, 2018, 7:18pm UTC](https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281/7 "2018-07-04T19:18:53Z")

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Flexbus is synchronous but very sensitive to logic delays.

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<div class="post-metadata">

**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [July 4, 2018, 7:22pm UTC](https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281/8 "2018-07-04T19:22:06Z")

</div>

However, I’m not trying to forcibly convince you to adopt my proposition.  
I expose an idea I had.  
We have ResetSignals which can be active high or active low. Why not have the same behavior for booleans ?

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<div class="post-metadata">

**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [July 5, 2018, 7:11am UTC](https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281/9 "2018-07-05T07:11:38Z")

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> [@DrPi](#):
>
> However, I’m not trying to forcibly convince you to adopt my proposition.  
> I expose an idea I had.

And I gave my opinion about it.

I think the proposed Bool() will have serious impact on simulation and conversion.  
The ResetSignal() is specifically aimed at decoupling the design from the actual physical implementation, making life easy. Its implementation is relatively simple as it is an _input only_ signal (at least I have never seen it at the LHS).  
Now you may say that the proposed Bool() will make life easy too. You may be very well right, and I just don’t see the light … (yet). In fact you may use my argument of _keeping everything internal_ active high against me.  
If you do proceed, can you make sure that statements like `cs.next = 1` also work? (I never use False or True) What about tristate signals?

So you almost won me over? Or did I do that myself? 🙂  
Regards,  
Josy

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<div class="post-metadata">

**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [July 5, 2018, 5:43pm UTC](https://discourse.myhdl.org/t/add-new-bool-type-to-myhdl/281/10 "2018-07-05T17:43:15Z")

</div>

> [@josyb](#):
>
> Now you may say that the proposed Bool() will make life easy too.

Correct

> [@josyb](#):
>
> In fact you may use my argument of _keeping everything internal_ active high against me.

Totaly agree on that 😉

> [@josyb](#):
>
> If you do proceed, can you make sure that statements like `cs.next = 1` also work? (I never use False or True)

Why should it be different from current bool ?

> [@josyb](#):
>
> What about tristate signals?

Well, tristate signals are tristate signals bools are bools (from MyHDL perspective).

> [@josyb](#):
>
> So you almost won me over? Or did I do that myself? 🙂

😄