# Convert FROM vhdl

**URL:** <https://discourse.myhdl.org/t/convert-from-vhdl/313>\
**Category:** Support\
**Created:** [July 19, 2018, 9:19am UTC](https://discourse.myhdl.org/t/convert-from-vhdl/313 "2018-07-19T09:19:38Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![mngr](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/mngr/32/96_2.png) [@mngr](https://discourse.myhdl.org/u/mngr)\
**Post date:** [July 19, 2018, 9:19am UTC](https://discourse.myhdl.org/t/convert-from-vhdl/313/1 "2018-07-19T09:19:39Z")

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Hi everyone,

I am very new here, an I would like to ask a couple a question:  
I am currently working on a project done in VHDL, and I want to port it to the open source toolchain made for Lattice FPGA.  
for what I know, that toolchain works only with verilog, so I will have to translate from vhdl to verilog.  
But, since I have to make a translation I can make it to myHDL.

Is it a good idea? is there any library that does this translation automatically?

Thanks in advance for any answer  
mngr

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**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [July 20, 2018, 11:36am UTC](https://discourse.myhdl.org/t/convert-from-vhdl/313/2 "2018-07-20T11:36:46Z")

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1. Ask the open source toolchain folks to implement the VHDL front-end!
2. Rewrite your VHDL code into MyHDL and have it generate Verilog (and VHDL to check/compare)

The options are not directly mutually exclusive 😄