# Cosimulation with verilator?

**URL:** <https://discourse.myhdl.org/t/cosimulation-with-verilator/417>\
**Category:** Enhancement Request\
**Created:** [March 13, 2020, 11:14am UTC](https://discourse.myhdl.org/t/cosimulation-with-verilator/417 "2020-03-13T11:14:23Z")\
**Posts on this page:** 1\
**Showing post:** 7

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**Author:** ![hgomersall](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/hgomersall/32/10_2.png) [@hgomersall](https://discourse.myhdl.org/u/hgomersall)\
**Post date:** [March 18, 2020, 11:26am UTC](https://discourse.myhdl.org/t/cosimulation-with-verilator/417/7 "2020-03-18T11:26:44Z")

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Yeah, we use Vivado extensively with MyHDL, and pretty much exclusively with the free version. Ovenbird is the tool we’ve created for verification. Also relevant might be [Kea](https://github.com/SmartAcoustics/Kea) which is useful tools that fit nicely into the Xilinx ecosystem, including a nice register subsystem.

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