# Creating a group of Signals

**URL:** <https://discourse.myhdl.org/t/creating-a-group-of-signals/487>\
**Category:** Uncategorized\
**Created:** [December 30, 2021, 9:13pm UTC](https://discourse.myhdl.org/t/creating-a-group-of-signals/487 "2021-12-30T21:13:34Z")\
**Posts on this page:** 6\
**Page:** 1

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**Author:** ![Mark](https://avatars.discourse-cdn.com/v4/letter/m/e9c0ed/32.png) [@Mark](https://discourse.myhdl.org/u/Mark)\
**Post date:** [December 30, 2021, 9:13pm UTC](https://discourse.myhdl.org/t/creating-a-group-of-signals/487/1 "2021-12-30T21:13:34Z")

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Is there a recommended MyHDL way to create a group of Signals?

In Python, I can declare a bunch of empty lists as:

`a,b,c = [],[],[]`

or

`a,b,c = [0]*16,[0]*8,[0,1,2]`

Is there a more concise way in Python to declare a bunch of lists?

(I have also used list comprehensions, and dedicated classes to do it, and am just looking for a more terse way to do it.)

In Verilog I might do something like:

`wire [31:0] a, b, c, d, e;`

or

`input [7:0] in1, in2` , etc.

In C++, I might model this using instances of a class Wire like:

`Wire32 a, b, c;`

In Python, if I were to use a class approach, one approach might be:

```auto
    a = Wire32() 
    b = Wire32() 
    c = Wire32() 

```

which seems a bit verbose to me. It gets even more complex when passing through MyHDL blocks. Still, I’m hoping this might be a reasonable simplification of the use case that might lead to relevant creative solutions.

My current solution is:

`a,b,c = [Wire(32) for i in range(3)]`

I do not like a couple things about this solution:

```auto
1. I have to count the number of elements which is cumbersome and error-prone
2. The definition is after the list which is unfamiliar to the "customer" who will likely be a hw engineer familiar with Verilog

```

(This is a duplicate of a Stack Overflow question that is currently unanswered: [python - Is there a more terse way to create a group of empty lists? - Stack Overflow](https://stackoverflow.com/questions/70466916/is-there-a-more-terse-way-to-create-a-group-of-empty-lists) )

I also found some information on creating MyHDL “Structures” of signals which could be a solution, but still having trouble wrapping my arms around it.

Here is an example of a post on interfaces that may lead to a good solution:

> <https://stackoverflow.com/questions/21087314/how-to-implement-interfaces-in-myhdl>

I’m sure there are other ways of creating classes to try create complex types, and then overload the operators, etc. for readability.

As always, thank you for your help as I try to learn the best practices in MyHDL!

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**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [January 1, 2022, 11:34am UTC](https://discourse.myhdl.org/t/creating-a-group-of-signals/487/2 "2022-01-01T11:34:55Z")

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My two pennies …  
`1.` using `a,b,c = [Signal(xxx) for __ in range(y)]` is what most MyHDL users will do. This creates a number of Signals of the same type and size.  
I personally only use this about once in every module. As you indicate one must keep count of the numbers, and this goes wrong at least once per day.  
As I use descriptive (sometimes long) names I prefer the _singular notation_ `pixelcountersclr = Signal(bool(0)`; it is just easier to re-read if you put each one on its own line  
I build _structural_ class-based designs where there are less _glue signals_ needed.

`2.` IMO will be less of a concern - the Verilog (or VHDL) engineer will learn.

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**Author:** ![Mark](https://avatars.discourse-cdn.com/v4/letter/m/e9c0ed/32.png) [@Mark](https://discourse.myhdl.org/u/Mark)\
**Post date:** [January 1, 2022, 7:51pm UTC](https://discourse.myhdl.org/t/creating-a-group-of-signals/487/3 "2022-01-01T19:51:50Z")

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Thanks again @Josyb–I agree with your points and feel better about moving on, now. Do you have any examples of the structures you mentioned?

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**Author:** ![hackfin](https://avatars.discourse-cdn.com/v4/letter/h/9d8465/32.png) [@hackfin](https://discourse.myhdl.org/u/hackfin)\
**Post date:** [January 3, 2022, 6:11pm UTC](https://discourse.myhdl.org/t/creating-a-group-of-signals/487/4 "2022-01-03T18:11:30Z")

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For creating lists of signals, there’s not much freedom beside what you’ve already tried.  
Obviously, the very compact `n * [element]` attempt will create a list of `n` references to `element`, thus ‘no such fun’ with mutable (!) Signals.  
The other native pythonic method is the MEP-107 one ([Conversion of Interfaces](https://dev.myhdl.org/meps/mep-107.html)), based on that you can write your own class factories taking some compact bulk signal descriptor as a dict, etc. This does not infer to an interface in the VHDL-2019 sense though, myhdl guesses in/output direction based on assignment of the member Signal and unrolls into single signals in the port description.

The meta-programming approach with the fancy operator overloading will however not just magically work with conversion to HDL, because the code is translated via AST-analysis. So, again ‘no such fun’ with generators (such as bulk signal assignments using `.next`), unless you’re in the _executed_ part of your HDL `@block` (outside the `@always*` functions). And there you’re limited to generating instances and signals, mostly.

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**Author:** ![Mark](https://avatars.discourse-cdn.com/v4/letter/m/e9c0ed/32.png) [@Mark](https://discourse.myhdl.org/u/Mark)\
**Post date:** [January 4, 2022, 3:38am UTC](https://discourse.myhdl.org/t/creating-a-group-of-signals/487/5 "2022-01-04T03:38:51Z")

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Thank you so much, @hackfin

Do you have any examples of your code I can peruse for best practices?

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**Author:** ![hackfin](https://avatars.discourse-cdn.com/v4/letter/h/9d8465/32.png) [@hackfin](https://discourse.myhdl.org/u/hackfin)\
**Post date:** [January 4, 2022, 11:12am UTC](https://discourse.myhdl.org/t/creating-a-group-of-signals/487/6 "2022-01-04T11:12:48Z")

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Put up a jupyter NB here: [myhdl\_class\_inheritance.ipynb · GitHub](https://gist.github.com/hackfin/5bbeda1524ffa2a9167d845556bb035d)  
It might be outdated but I’ve just run it against a recent myhdl 0.11 w/o unexpected issues. Should also upload and run in a jupyterhub binder, as [GitHub - hackfin/hdlplayground: Document, build and simulate hardware designs (MyHDL, VHDL, Verilog)](https://github.com/hackfin/hdlplayground/).

Should also mention that the blackbox stuff was an experiment, so you may ignore that for the time being. A fully functional design would require to add some HW description for the UUT in this example.