# Don't care / unknown

**URL:** <https://discourse.myhdl.org/t/dont-care-unknown/368>\
**Category:** Support\
**Created:** [March 21, 2019, 6:02pm UTC](https://discourse.myhdl.org/t/dont-care-unknown/368 "2019-03-21T18:02:12Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![philn16](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/philn16/32/103_2.png) [@philn16](https://discourse.myhdl.org/u/philn16)\
**Post date:** [March 21, 2019, 6:02pm UTC](https://discourse.myhdl.org/t/dont-care-unknown/368/1 "2019-03-21T18:02:12Z")

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Is there a way of assigning a variable a don’t care / unknown type in MyHDL?  
For example, in verilog I’d write  
wire [3:0]dontcare=4’bxxxx;

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [March 22, 2019, 7:33am UTC](https://discourse.myhdl.org/t/dont-care-unknown/368/2 "2019-03-22T07:33:10Z")

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What are you trying to achieve ?

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**Author:** ![philn16](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/philn16/32/103_2.png) [@philn16](https://discourse.myhdl.org/u/philn16)\
**Post date:** [March 26, 2019, 12:03am UTC](https://discourse.myhdl.org/t/dont-care-unknown/368/3 "2019-03-26T00:03:46Z")

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My current primary motivation is I like to assign invalid data don’t cares since it makes reading waveform diagrams easier. For example, in an AXI stream if valid is 0 I like to make data a don’t care vector. However, there are lots of other reasons you’d want don’t cares.

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [March 28, 2019, 9:54am UTC](https://discourse.myhdl.org/t/dont-care-unknown/368/4 "2019-03-28T09:54:49Z")

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Here is a way to manage signals with an _unknown value_ :

```python
from myhdl import block, Signal, TristateSignal, intbv, always_seq

@block
def dut(i_clk, i_din, i_en, o_dout):

    @always_seq(i_clk.posedge, None)
    def regout():
        if i_en :
            o_dout.next = i_din
        else :
            o_dout.next = None
        
    return regout

@block
def simulate_dut():
    from myhdl import instance, always, delay, StopSimulation
    
    i_clk = Signal(bool(0))
    i_en = Signal(bool(0))
    i_din = Signal(intbv(0)[8:])
    o_dout = TristateSignal(intbv(0)[8:]) # Create Tri-state signal
    dout = o_dout.driver() # Get a driver for the tri-state signal

    dut_inst = dut(i_clk, i_din, i_en, dout)

    @always(delay(16//2))
    def clk_gen():
        i_clk.next = not i_clk

    def delay_clk(clk, dly) :
        for _ in range(dly) :
            yield clk.posedge
            
    @instance
    def inputs_gen() :
        yield delay_clk(i_clk, 20)
        i_en.next = True
        yield delay_clk(i_clk, 20)
        i_en.next = False
        yield delay_clk(i_clk, 10)
        i_din.next = 0xA5
        yield delay_clk(i_clk, 20)
        i_en.next = True
        yield delay_clk(i_clk, 10)
        i_din.next = 0x5A
        yield delay_clk(i_clk, 20)
        i_en.next = False
        yield delay_clk(i_clk, 20)
        raise StopSimulation()
        
    return dut_inst, clk_gen, inputs_gen

def simulate():
    tb = simulate_dut()
    tb.config_sim(trace=True, timescale='1ns', directory=".", tracebackup=False)
    tb.run_sim()
    
if __name__ == " __main__" :
    simulate()
    print("Done")

```

Simulation result :

 ![image](https://canada1.discourse-cdn.com/flex030/uploads/myhdl/original/1X/72caab06d4a567b298b7009f98375ee5b036f60c.png)

Beware that **high impedance** signals are **not supported** for long time in modern FPGAs (except for I/O signals).

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<div class="post-metadata">

**Author:** ![philn16](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/philn16/32/103_2.png) [@philn16](https://discourse.myhdl.org/u/philn16)\
**Post date:** [March 28, 2019, 11:15pm UTC](https://discourse.myhdl.org/t/dont-care-unknown/368/5 "2019-03-28T23:15:17Z")

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Thanks for the tip and example. I think this might supplement what I want.