# Error in the converted verilog code
**URL:** https://discourse.myhdl.org/t/error-in-the-converted-verilog-code/88
**Category:** Support
**Created:** [June 15, 2016, 5:43pm UTC](https://discourse.myhdl.org/t/error-in-the-converted-verilog-code/88 "2016-06-15T17:43:09Z")
**Posts on this page:** 9
**Page:** 1
### Author:  [@Ravi\_Jain](https://discourse.myhdl.org/u/Ravi_Jain)
#### Post date: [June 15, 2016, 5:43pm UTC](https://discourse.myhdl.org/t/error-in-the-converted-verilog-code/88/1 "2016-06-15T17:43:09Z")
[1.In](http://1.In) the converted code, On reset the initial values are assigned improperly.
MyHDL snippet:
```
self.rdindex = Signal(intbv(17, min=0, max=18))
self.wrindex = Signal(intbv(62, min=0, max=63))
```
Verilog code snippet:
```
management_6_mdiodata_rdindex <= 11;
management_6_mdiodata_wrindex <= 3e;
```
The values assigned in the verilog code are in hex so the correct code should be
```
management_6_mdiodata_rdindex <= 'h11;
management_6_mdiodata_wrindex <= 'h3e;
```
1. The below conversion flags an syntax error due to [32-1:0] in the end.
MyHDl snippet:
```
mdiodata.wrdata.next = concat(intbv(0b01)[2:], host_interface.opcode[2:],
host_interface.regaddress[10:], intbv(0b10)[2:],
host_interface.wrdata[16:])[32:]
```
Converted Verilog snippet:
```
management_6_mdiodata_wrdata <= {2'h1, management_6_host_interface_opcode[2-1:0], management_6_host_interface_regaddress[10-1:0], 2'h2, management_6_host_interface_wrdata[16-1:0]}[32-1:0];
```
Workaround:
```
wrdata = concat(intbv(0b01)[2:], host_interface.opcode[2:],
host_interface.regaddress[10:], intbv(0b10)[2:],
host_interface.wrdata[16:])
mdiodata.wrdata.next = wrdata[32:]
```
---
### Author:  [@josyb](https://discourse.myhdl.org/u/josyb)
#### Post date: [June 16, 2016, 12:14pm UTC](https://discourse.myhdl.org/t/error-in-the-converted-verilog-code/88/2 "2016-06-16T12:14:50Z")
HI Ravi,
that’s _two_ issues in _one_ 🙂
I can’t help much on the first (Verilog is not my thing …)
The second:
You don’t need to append the _[32:]_ slicing operation if the width of the _concat_ result is equal to 32.
---
### Author:  [@cfelton](https://discourse.myhdl.org/u/cfelton)
#### Post date: [June 16, 2016, 12:55pm UTC](https://discourse.myhdl.org/t/error-in-the-converted-verilog-code/88/3 "2016-06-16T12:55:30Z")
This little snippet demonstrates two problems, first the literal generation for the reset assignment that @Ravi_Jain stumbled upon. Second, the odd signal state issue @hgomersall describes in #176. The second is more of an annoyance with the incorrect
warning message.
```python
import myhdl
from myhdl import Signal, ResetSignal, intbv, always_seq
@myhdl.block
def myblock(clock, reset, inc, out):
rdindex = Signal(intbv(17, min=0, max=18))
wrindex = Signal(intbv(62, min=0, max=63))
@always_seq(clock.posedge, reset=reset)
def beh():
out.next = rdindex + wrindex
if inc:
rdindex.next = rdindex + 1
wrindex.next = wrindex + 1
return beh
clock = Signal(bool(0))
reset = ResetSignal(0, active=1, async=False)
inc = Signal(bool(0))
out = Signal(intbv(0)[32:0])
inst = myblock(clock, reset, inc, out)
inst.convert(hdl='Verilog')
inst.convert(hdl='VHDL')
```
### Converted Verilog
```auto
// File: myblock.v
// Generated by MyHDL 1.0dev
// Date: Thu Jun 16 07:48:50 2016
`timescale 1ns/10ps
module myblock (
clock,
reset,
inc,
out
);
input clock;
input reset;
input inc;
output [31:0] out;
reg [31:0] out;
reg [4:0] rdindex;
reg [5:0] wrindex;
always @(posedge clock) begin: MYBLOCK_BEH
if (reset == 1) begin
wrindex <= 3e;
out <= 00000000;
rdindex <= 11;
end
else begin
out <= (rdindex + wrindex);
if (inc) begin
rdindex <= (rdindex + 1);
wrindex <= (wrindex + 1);
end
end
end
endmodule
```
### Converted VHDL
```auto
-- File: myblock.vhd
-- Generated by MyHDL 1.0dev
-- Date: Thu Jun 16 07:49:34 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity myblock is
port (
clock: in std_logic;
reset: in std_logic;
inc: in std_logic;
out: out unsigned(31 downto 0)
);
end entity myblock;
architecture MyHDL of myblock is
signal rdindex: unsigned(4 downto 0);
signal wrindex: unsigned(5 downto 0);
begin
MYBLOCK_BEH: process (clock) is
begin
if rising_edge(clock) then
if (reset = '1') then
wrindex <= to_unsigned(3e, 6);
out <= to_unsigned(00000000, 32);
rdindex <= to_unsigned(11, 5);
else
out <= (resize(rdindex, 32) + wrindex);
if bool(inc) then
rdindex <= (rdindex + 1);
wrindex <= (wrindex + 1);
end if;
end if;
end if;
end process MYBLOCK_BEH;
end architecture MyHDL;
```
@Ravi_Jain can you create a test for this and create a PR to the myhdl repository. See @sriramesh4 [test](https://github.com/jandecaluwe/myhdl/pull/170) as an example.
---
### Author:  [@josyb](https://discourse.myhdl.org/u/josyb)
#### Post date: [June 16, 2016, 2:02pm UTC](https://discourse.myhdl.org/t/error-in-the-converted-verilog-code/88/4 "2016-06-16T14:02:54Z")
It did work OK some commits ago …
If I run @cfelton’s through my local MyHDL library I get correct behaviour:
Verilog:
```auto
always @(posedge clock) begin: myblock_beh
if (reset == 1) begin
outp <= 0;
rdindex <= 17;
wrindex <= 62;
end
```
VHDL:
```auto
beh : process(clock) is
begin
if rising_edge(clock) then
if (reset = '1') then
outp <= to_unsigned(0, 32);
rdindex <= to_unsigned(17, 5);
wrindex <= to_unsigned(62, 6);
else
```
And I didn’t get any warning.
---
### Author:  [@cfelton](https://discourse.myhdl.org/u/cfelton)
#### Post date: [June 16, 2016, 2:12pm UTC](https://discourse.myhdl.org/t/error-in-the-converted-verilog-code/88/5 "2016-06-16T14:12:59Z")
I think (not sure) it was broke when some ~~minor~~ changes were made to support IVS, specifically the larger than 32bit initial values.
I think [this is the change](https://github.com/jandecaluwe/myhdl/blame/master/myhdl/_intbv.py#L483) that broke it. It was the unforeseen downstream that didn’t create the correct literal format.
This is a perfect task for @Ravi_Jain, to create a myhdl test in the bugs and expand the `always_seq` conversion tests in `test/conversion/general` (actually, since this is still 1.0dev I guess we don’t create a bug test but rather increase the test suite coverage).
The fix would be to make sure the init representation is a hex string always and then modify the V\* writes to format correctly.
---
### Author:  [@Ravi\_Jain](https://discourse.myhdl.org/u/Ravi_Jain)
#### Post date: [June 16, 2016, 2:40pm UTC](https://discourse.myhdl.org/t/error-in-the-converted-verilog-code/88/6 "2016-06-16T14:40:23Z")
Yep i will get onto it.
---
### Author:  [@Ravi\_Jain](https://discourse.myhdl.org/u/Ravi_Jain)
#### Post date: [June 16, 2016, 2:48pm UTC](https://discourse.myhdl.org/t/error-in-the-converted-verilog-code/88/7 "2016-06-16T14:48:23Z")
@ 2nd problem
Still if i want to slice it in an unorthodox way like, [30:16], etc. The Conversion should take care of it, right? Throw up some error or Warning at least.
---
### Author:  [@josyb](https://discourse.myhdl.org/u/josyb)
#### Post date: [June 16, 2016, 3:05pm UTC](https://discourse.myhdl.org/t/error-in-the-converted-verilog-code/88/8 "2016-06-16T15:05:56Z")
VHDL will take that.
I don’t know about Verilog but it may be that you can’t slice a _{ concatenation }_. I’ll (try to) check that.
---
### Author:  [@josyb](https://discourse.myhdl.org/u/josyb)
#### Post date: [June 16, 2016, 5:59pm UTC](https://discourse.myhdl.org/t/error-in-the-converted-verilog-code/88/9 "2016-06-16T17:59:36Z")
@Ravi_Jain
I was wrong, it doesn’t work in VHDL either.
```auto
outp <= (to_unsigned(0, 21) & rdindex & wrindex)(31 downto 0);
```
ModelSim complains:
```auto
** Error: C:\Users\Josy\workspace-CC-Logic\Experiments\rj\myblock.vhd(58): near "(": (vcom-1576) expecting ';'.
```
And for this Verilog code:
```auto
outp <= {21'h0, rdindex, wrindex}[32-1:0];
```
ModelSIm claims:
```auto
** Error: C:\Users\Josy\workspace-CC-Logic\Experiments\rj\myblock.v(35): Illegal part-select expression
```
Looks like your workaround, using an intermediate signal, is the best option. I can think of a way to do this in VHDL, but don’t know Verilog well enough to even have an idea.