# First attempt with MyHDL

**URL:** <https://discourse.myhdl.org/t/first-attempt-with-myhdl/472>\
**Category:** Uncategorized\
**Created:** [September 15, 2021, 11:52am UTC](https://discourse.myhdl.org/t/first-attempt-with-myhdl/472 "2021-09-15T11:52:38Z")\
**Posts on this page:** 2\
**Page:** 1

<div class="post-metadata">

**Author:** ![Albert](https://avatars.discourse-cdn.com/v4/letter/a/48db29/32.png) [@Albert](https://discourse.myhdl.org/u/Albert)\
**Post date:** [September 15, 2021, 11:52am UTC](https://discourse.myhdl.org/t/first-attempt-with-myhdl/472/1 "2021-09-15T11:52:38Z")

</div>

In a first attempt to use MyHDL I converted some VHDL lines to MyHDL. I tried to do this as good as possible. Because I want to use MyHDL for building reference models and use them in a VHDL testbench, I tried to convert the Python lines to VHDL. I got some error message which I can not get solved. I probably made some stupid (beginners) errors. Can someone tell me what is wrong with my code?

_emphasized text_  
from myhdl import block, instance, always\_seq, toVHDL, Signal

@block  
def cropper(ip\_rst, ip\_clk, I2F\_image\_to\_cropper, I2F\_image\_from\_cropper, I2F\_wait\_to\_cropper, I2F\_wait\_from\_cropper, Cropperprm, ResetError):

# To avoid the header fifo being read before the first header word has rippled through

# an extra register delay is added in the cropper processing pipe (Header fifo ripple requires 3 clocks)

@instance  
def register\_buffer(ip\_clk, ResetError, dHold, Input):

# BufferOutput\_Format = intbv(0, min=0, max=16) # from min to max-1

# BufferOutput\_Data = intbv(0, min=0, max=65536) # from min to max-1

# BufferOutput\_Defect = intbv(0, min=0, max=2) # from min to max-1

```
@always_seq(ip_clk.posedge)
def RegisterBuffer():
  if ResetError == 1:
    BufferOutput.Format = c_IDLE
    BufferOutput.Data = 0
    BufferOutput.Defect = 0
  elif dHold == 0:
    BufferOutput.Format = Input.Format
    BufferOutput.Data = Input.Data
    BufferOutput.Defect = Input.Defect
    
return RegisterBuffer    

```

@instance  
def Wait\_to\_prev(ip\_clk, ip\_rst):

```
if ip_rst == 1:
  dHold = 0

@always_seq(ip_clk.posedge)
def wait():
  dHold = WaitIn

return dHold    

```

def convert\_cropper(hdl):  
#assign default/initial values to signals

# 

ip\_rst = Signal(bool(1)) # 1 = default/initial value  
ip\_clk = Signal(bool(0))  
BufferOutput = Signal(int(0))  
I2F\_image\_to\_cropper = Signal(int(0))  
I2F\_image\_from\_cropper = Signal(int(0))  
I2F\_wait\_to\_cropper = Signal(bool(0))  
I2F\_wait\_from\_cropper = Signal(bool(0))  
Cropperprm = Signal(int(0))  
ResetError = Signal(bool(0))

inc\_1 = cropper(ip\_rst, ip\_clk, I2F\_image\_to\_cropper, I2F\_image\_from\_cropper, I2F\_wait\_to\_cropper, I2F\_wait\_from\_cropper, Cropperprm, ResetError)  
inc\_1.convert(hdl)

convert\_cropper(hdl=‘VHDL’)

---

<div class="post-metadata">

**Author:** ![Albert](https://avatars.discourse-cdn.com/v4/letter/a/48db29/32.png) [@Albert](https://discourse.myhdl.org/u/Albert)\
**Post date:** [September 16, 2021, 1:25pm UTC](https://discourse.myhdl.org/t/first-attempt-with-myhdl/472/2 "2021-09-16T13:25:53Z")

</div>

After a lot of changes I managed to convert my first MyHDL code to VHDL. My code contained a lot of errors. Still a lot to learn!