# From myHDL to syntesis

**URL:** <https://discourse.myhdl.org/t/from-myhdl-to-syntesis/323>\
**Category:** Support\
**Created:** [August 3, 2018, 9:53am UTC](https://discourse.myhdl.org/t/from-myhdl-to-syntesis/323 "2018-08-03T09:53:29Z")\
**Posts on this page:** 9\
**Page:** 1

<div class="post-metadata">

**Author:** ![mngr](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/mngr/32/96_2.png) [@mngr](https://discourse.myhdl.org/u/mngr)\
**Post date:** [August 3, 2018, 9:53am UTC](https://discourse.myhdl.org/t/from-myhdl-to-syntesis/323/1 "2018-08-03T09:53:29Z")

</div>

Hi everyone,  
I am very new in the FGPA world, and I am making the first steps.  
I have a little myHDL program and I am trying to synthesize it. (converting to Verilog, then using icestorm)  
the simulation works as intended, and I want to move it in the FPGA.  
I added the input output pin in the verilog, any way to do it in myhdl?  
now icestorm is giving me an error…  
is there any procedure that I should follow? because now I am doing pretty random things…  
Thansk to anyone who help me  
mngr0

---

<div class="post-metadata">

**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [August 3, 2018, 10:04am UTC](https://discourse.myhdl.org/t/from-myhdl-to-syntesis/323/2 "2018-08-03T10:04:22Z")

</div>

You are advised to post the code. So we can give you ‘directed’ help.

---

<div class="post-metadata">

**Author:** ![mngr](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/mngr/32/96_2.png) [@mngr](https://discourse.myhdl.org/u/mngr)\
**Post date:** [August 3, 2018, 10:39am UTC](https://discourse.myhdl.org/t/from-myhdl-to-syntesis/323/4 "2018-08-03T10:39:37Z")

</div>

[https://github.com/mngr0/test](https://github.com/mngr0/test)

here, I have made a repo with the files.  
fpga25\_snip4.py and test\_stroby.py are the files in myHDL  
test\_random.v is the verilog generated file  
and in test\_random\_corrected.v i have made some changes that make it compile.  
I feel that after my changes I should re-simulate.

then there is a makefile and example-8k.pcf that declares the connection between signals and pins.

---

<div class="post-metadata">

**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [August 3, 2018, 3:42pm UTC](https://discourse.myhdl.org/t/from-myhdl-to-syntesis/323/5 "2018-08-03T15:42:24Z")

</div>

I made a PullRequest with some small changes … you were close

---

<div class="post-metadata">

**Author:** ![mngr](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/mngr/32/96_2.png) [@mngr](https://discourse.myhdl.org/u/mngr)\
**Post date:** [August 4, 2018, 10:06am UTC](https://discourse.myhdl.org/t/from-myhdl-to-syntesis/323/6 "2018-08-04T10:06:06Z")

</div>

Thanks!! obviously I have to give input and output to the block! Thank you very much!

---

<div class="post-metadata">

**Author:** ![mngr](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/mngr/32/96_2.png) [@mngr](https://discourse.myhdl.org/u/mngr)\
**Post date:** [August 4, 2018, 1:21pm UTC](https://discourse.myhdl.org/t/from-myhdl-to-syntesis/323/7 "2018-08-04T13:21:15Z")

</div>

Hi,

I am sorry, but I have to ask for help again:  
I made a couple of examples in my repo: blink and shift.  
blink blinks but shift doesn’t shifts, yesterday I thought it was an issue with the pcf file, but the same pcf with blink works.  
The myHDL code seems fine, and the simulation agrees, but the FPGA disagree… can you please give another look?  
mngr0

---

<div class="post-metadata">

**Author:** ![mngr](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/mngr/32/96_2.png) [@mngr](https://discourse.myhdl.org/u/mngr)\
**Post date:** [August 6, 2018, 9:02am UTC](https://discourse.myhdl.org/t/from-myhdl-to-syntesis/323/8 "2018-08-06T09:02:49Z")

</div>

I got it! It was an initialization problem!  
the translation to verilog forget to assign the initial value… should I write the myHDL code in a different way?

---

<div class="post-metadata">

**Author:** ![mngr](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/mngr/32/96_2.png) [@mngr](https://discourse.myhdl.org/u/mngr)\
**Post date:** [August 6, 2018, 9:09am UTC](https://discourse.myhdl.org/t/from-myhdl-to-syntesis/323/9 "2018-08-06T09:09:30Z")

</div>

sorry, I should study before writing.  
tr.convert(‘Verilog’,initial\_values=True)  
that’s it

---

<div class="post-metadata">

**Author:** ![theller](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/theller/32/92_2.png) [@theller](https://discourse.myhdl.org/u/theller)\
**Post date:** [August 7, 2018, 8:33am UTC](https://discourse.myhdl.org/t/from-myhdl-to-syntesis/323/10 "2018-08-07T08:33:10Z")

</div>

Hehe - Interesting.

I’m a long-time myhdl user. I was waiting for initial\_value support for quite some time.  
I did not always follow the discussions but always read the “what’s new” sections in the manual.

However, this is the fist time that I found that initial value support is implemented.

Why isn’t this menioned in the manual?  
Do I have to read the source code to find out what’s implemented?

Thomas