Hello, new myhdl user here. I’ve hit my first hurdle that I haven’t been able to solve perusing the many excellent examples out there. In fact, I’ve seen others with similar problem but haven’t seen a resolution. I initially posted in in issue #161 and later found this forum which is probably a better place for my question:
I’ve seen in a few places (issues #161 & #181 that “Conversion of List of Signals for a top-level block is not supported.”
I’ve tried to work around this by creating a top() wrapper which doesn’t have a list of signals but conversion still fails (presumably since I have a list of signals in a lower level of hierarchy & I mis-understand what top-level block means).
Since it doesn’t appear that list of signal conversion will be supported anytime soon (I’ve seen conversations on this dating back over a decade: https://sourceforge.net/p/myhdl/mailman/message/18646379/ ), what is the best way to handle this situation? I’m really enjoying writing in myhdl but will have this situation often as my designs are hierarchical where I often need to assign to individual bits of a bus.
Here’s a simple example: I define a “dff” then want to create a bank of them in a block named “registers”. Below is the syntax that I had to use to get it to simulate correctly but am unsure how I can convert this to verilog. Calling either convert_register() or convert_top() results in the same error:
myhdl.ConversionError: in file issue_161.py, line 37: # line 37 is the ConcatSignal line Not supported: extra positional arguments
A working example of how to handle this situation (for verilog conversion) would be greatly appreciated. Below is my simplified code.
@block def dff(clk, d, q): @always(clk.posedge) def logic(): q.next = d return logic @block def registers(clk, d, q): """ bank of 8 dff's """ insts =  # need to create a temporary storage for q's b/c shadow sig is read-only qs = [Signal(bool(0)) for _ in range(len(q))] for i in range(len(d)): inst = dff(clk, d(i), qs[i]) inst.name = 'dff%d' % i insts.append(inst) # Concatenate the qs bits and send them out on the q output. @always_comb def make_q(): q.next = ConcatSignal(*reversed(qs)) return insts, make_q @block def top(): """ Dummy level of hierarchy to see if it will convert """ n_bits = 8 clk = Signal(bool(0)) d = Signal(intbv(0)[n_bits:]) q = Signal(intbv(0)[n_bits:]) inst = registers(clk, d, q) return inst def convert_register(): n_bits = 8 clk = Signal(bool(0)) d = Signal(intbv(0)[n_bits:]) q = Signal(intbv(0)[n_bits:]) toVerilog(registers(clk, d, q)) def convert_top(): toVerilog(top())