# How to infer to unique case

**URL:** <https://discourse.myhdl.org/t/how-to-infer-to-unique-case/458>\
**Category:** Support\
**Created:** [March 12, 2021, 9:35am UTC](https://discourse.myhdl.org/t/how-to-infer-to-unique-case/458 "2021-03-12T09:35:30Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Logan](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/logan/32/142_2.png) [@Logan](https://discourse.myhdl.org/u/Logan)\
**Post date:** [March 12, 2021, 9:35am UTC](https://discourse.myhdl.org/t/how-to-infer-to-unique-case/458/1 "2021-03-12T09:35:31Z")

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I checked the FSM and found it inferred casez:  
casez (state)  
3’b??1: …  
3’b?1?: …  
3’b1??: …  
This coding style is forbidden by us, since it will infer prioritize case(just like if-else), and casez will may generate bug if some signal really have value of Z.

I think system verilog already provide unique case and full case, how to generate such code?

Furthermore, can I define some rules to constraint the code generation to verilog?

Thanks.  
Logan.

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**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [March 12, 2021, 10:53am UTC](https://discourse.myhdl.org/t/how-to-infer-to-unique-case/458/2 "2021-03-12T10:53:08Z")

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Dear Logan,

I agree that the `casez` is not suited. I have a PullRequest #357 to use the standard `case` instead.  
But unfortunately we have to wait for it to be merged.

Best regards,  
Josy