# How to pass part of the signal to module

**URL:** <https://discourse.myhdl.org/t/how-to-pass-part-of-the-signal-to-module/186>\
**Category:** Support\
**Created:** [May 12, 2017, 2:48pm UTC](https://discourse.myhdl.org/t/how-to-pass-part-of-the-signal-to-module/186 "2017-05-12T14:48:49Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![lamazavr](https://avatars.discourse-cdn.com/v4/letter/l/7ab992/32.png) [@lamazavr](https://discourse.myhdl.org/u/lamazavr)\
**Post date:** [May 12, 2017, 2:48pm UTC](https://discourse.myhdl.org/t/how-to-pass-part-of-the-signal-to-module/186/1 "2017-05-12T14:48:49Z")

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Hi,  
I have module:

> def addsub(clk, add, a, b, q):

> ```
> @always(clk.posedge)
> def addsub_logic():
> if add == 1:
> q.next = a + b
> else:
> q.next = a - b
> 
> ```

> ```
> return addsub_logic
> 
> ```

I want to create main module that will drive multiple instancies of addsub.  
I need to slice d parameter and pass it to submodules. But how?  
The example below doesn’t work.

```
def main(clk, d, q):
    res_l_0 = Signal(intbv(0, min=0, max=2**3))
    addsub_inst_0 = addsub(clk, intbv("1"), d[31:29], intbv("001"), res_l_0)

    res_l_1 = Signal(intbv(0, min=0, max=2**4))
    addsub_inst_1 = addsub(clk, res_l_0[2], d[29:27], concat("1", res_l_0[2], res_l_0[2], bool(0)), res_l_1)

```

---

<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [May 12, 2017, 10:07pm UTC](https://discourse.myhdl.org/t/how-to-pass-part-of-the-signal-to-module/186/2 "2017-05-12T22:07:21Z")

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I didn’t review your example in detail but [this might help](http://docs.myhdl.org/en/stable/manual/structure.html#converting-between-lists-of-signals-and-bit-vectors)

---

<div class="post-metadata">

**Author:** ![pythondsp](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/pythondsp/32/74_2.png) [@pythondsp](https://discourse.myhdl.org/u/pythondsp)\
**Post date:** [October 13, 2017, 7:17pm UTC](https://discourse.myhdl.org/t/how-to-pass-part-of-the-signal-to-module/186/3 "2017-10-13T19:17:34Z")

</div>

An example of passing the part of ports is added at the below link,  
[http://fpga-designs-with-myhdl.readthedocs.io/en/latest/myhdl/overview.html#structural-modeling](http://fpga-designs-with-myhdl.readthedocs.io/en/latest/myhdl/overview.html#structural-modeling)

In comparator\_2\_bit\_struct.py, following lines are used to pass the part of the signal to two different instances.

```auto
    # instantiation : 1-bit comparator
    eq0 = comparator_1_bit_proc(x=a(0), y=b(0), eq=s0)
    eq1 = comparator_1_bit_proc(x=a(1), y=b(1), eq=s1)

```