# I need counter 4-bit please help me

**URL:** <https://discourse.myhdl.org/t/i-need-counter-4-bit-please-help-me/413>\
**Category:** Uncategorized\
**Created:** [February 11, 2020, 10:25am UTC](https://discourse.myhdl.org/t/i-need-counter-4-bit-please-help-me/413 "2020-02-11T10:25:45Z")\
**Posts on this page:** 8\
**Page:** 1

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**Author:** ![reza.ahadi](https://avatars.discourse-cdn.com/v4/letter/r/b38774/32.png) [@reza.ahadi](https://discourse.myhdl.org/u/reza.ahadi)\
**Post date:** [February 11, 2020, 10:25am UTC](https://discourse.myhdl.org/t/i-need-counter-4-bit-please-help-me/413/1 "2020-02-11T10:25:45Z")

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hi  
I need counter 4-bit with up count and down count in myhdl and convert to verilog or vhdl.  
please help me

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [February 12, 2020, 8:09am UTC](https://discourse.myhdl.org/t/i-need-counter-4-bit-please-help-me/413/2 "2020-02-12T08:09:12Z")

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Hi,  
To get help, you need to provide detailed information. Do you have a sample design to submit ?

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<div class="post-metadata">

**Author:** ![reza.ahadi](https://avatars.discourse-cdn.com/v4/letter/r/b38774/32.png) [@reza.ahadi](https://discourse.myhdl.org/u/reza.ahadi)\
**Post date:** [February 12, 2020, 4:12pm UTC](https://discourse.myhdl.org/t/i-need-counter-4-bit-please-help-me/413/3 "2020-02-12T16:12:08Z")

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#I wrote this program but I don’t know where I’m wrong

from myhdl import \*

ACTIVE, INACTIVE = bool(0), bool(1)

DOWN,UP, stop, clk , q = [Signal(INACTIVE) for i in range(5)]

DirType = enum(‘UP’, ‘DOWN’)

def counter(DOWN,UP, stop, clk, q):

```
I/O pins:
--------

clk : input free-running clock 
goDown : input signal to down (active-low switch)
goUp : input signal to up (active-low switch)
stop : input signal to stop counting (active-low switch)
q : 4-bit counter output 

@instance
def logic():
    dir = DirType. __reduce__
    run = False
    while True:
        yield clk.posedge
        # direction
        if UP == ACTIVE:
            dir = DirType. __init__
            run = True
        elif DOWN == ACTIVE:
            dir = DirType. __reduce__
            run = True
        # stop
        if stop == ACTIVE:
            run = False
        # counter action
        if run:
            if dir == DirType.__reduce:
                q.next = q-1 
                
           
            else :       
               q.next = q+1 
             

return logic

```

counter = counter(DOWN,UP, stop, clk, q)  
counter.convert(hdl=“Verilog”, initial\_values=True)

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<div class="post-metadata">

**Author:** ![reza.ahadi](https://avatars.discourse-cdn.com/v4/letter/r/b38774/32.png) [@reza.ahadi](https://discourse.myhdl.org/u/reza.ahadi)\
**Post date:** [February 12, 2020, 4:19pm UTC](https://discourse.myhdl.org/t/i-need-counter-4-bit-please-help-me/413/5 "2020-02-12T16:19:12Z")

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And also this app:  
from random import randrange  
from myhdl import \*

ACTIVE\_LOW, INACTIVE\_HIGH = 0, 1

def Inc(count, down, enable, clock, reset):

```
@always_seq(clock.posedge, reset=reset)
def incLogic():
    if enable:
        count.next = count+1
    if down:
        count.next = count-1 

return incLogic

```

# conversion

m = 4

count = Signal(modbv(0)[m:])  
down = Signal(bool(0))  
enable = Signal(bool(0))  
clock = Signal(bool(0))  
reset = ResetSignal(0, active=0, isasync=True)  
n=Signal(modbv(0)[3:])

counter\_verilog = inc(count, down, enable, clock, reset)  
counter\_verilog.convert(hdl=“Verilog”, initial\_values=True)

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<div class="post-metadata">

**Author:** ![reza.ahadi](https://avatars.discourse-cdn.com/v4/letter/r/b38774/32.png) [@reza.ahadi](https://discourse.myhdl.org/u/reza.ahadi)\
**Post date:** [February 12, 2020, 4:21pm UTC](https://discourse.myhdl.org/t/i-need-counter-4-bit-please-help-me/413/6 "2020-02-12T16:21:19Z")

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I want to count from (0000) to (1111)  
with up count and down count

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<div class="post-metadata">

**Author:** ![hgomersall](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/hgomersall/32/10_2.png) [@hgomersall](https://discourse.myhdl.org/u/hgomersall)\
**Post date:** [February 13, 2020, 11:00am UTC](https://discourse.myhdl.org/t/i-need-counter-4-bit-please-help-me/413/7 "2020-02-13T11:00:50Z")

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So what happens when you run it? I assume you’ve written some kind of test to exercise it?

Also, I suggest working a bit more on your code formatting on discourse, which is a little hard to read.

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<div class="post-metadata">

**Author:** ![reza.ahadi](https://avatars.discourse-cdn.com/v4/letter/r/b38774/32.png) [@reza.ahadi](https://discourse.myhdl.org/u/reza.ahadi)\
**Post date:** [February 13, 2020, 11:08am UTC](https://discourse.myhdl.org/t/i-need-counter-4-bit-please-help-me/413/8 "2020-02-13T11:08:38Z")

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It generally does not convert to vhdl or verilog.

If you can, send me the counter code.

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<div class="post-metadata">

**Author:** ![JanCoombs](https://avatars.discourse-cdn.com/v4/letter/j/9fc29f/32.png) [@JanCoombs](https://discourse.myhdl.org/u/JanCoombs)\
**Post date:** [February 17, 2020, 9:22am UTC](https://discourse.myhdl.org/t/i-need-counter-4-bit-please-help-me/413/9 "2020-02-17T09:22:19Z")

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There are two adder designs with test code here [https://rosettacode.org/wiki/Four\_bit\_adder#MyHDL](https://rosettacode.org/wiki/Four_bit_adder#MyHDL) perhaps you could base your work on one of these?