# Moving to 0.1dev broke my design

**URL:** <https://discourse.myhdl.org/t/moving-to-0-1dev-broke-my-design/259>\
**Category:** Support\
**Created:** [March 22, 2018, 10:39pm UTC](https://discourse.myhdl.org/t/moving-to-0-1dev-broke-my-design/259 "2018-03-22T22:39:49Z")\
**Posts on this page:** 2\
**Page:** 1

<div class="post-metadata">

**Author:** ![kc64](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/kc64/32/83_2.png) [@kc64](https://discourse.myhdl.org/u/kc64)\
**Post date:** [March 22, 2018, 10:39pm UTC](https://discourse.myhdl.org/t/moving-to-0-1dev-broke-my-design/259/1 "2018-03-22T22:39:49Z")

</div>

I updated my version of MyHDL and my code broke. It looks like conversion to .v worked but the test/simulation failed. After spending hours on the forums, I have not recovered that part yet.

This is what worked end-to-end in v0.9.

```
from myhdl import *

CLOCK = 40
HALF_CLOCK = delay(int(CLOCK / 2))
WIDTH = 32

def counter(clock, reset, clear, enable, count):

    @always(clock.posedge, reset.posedge)
    def logic():

        if reset or clear:
            count.next = 0
        elif enable:
            count.next = count + 1

    return logic

def test():

    clock = Signal(bool(0))
    reset = Signal(bool(0))
    clear = Signal(bool(0))
    enable = Signal(bool(0))
    count = Signal(intbv(0)[WIDTH:0])

    inst = counter(clock, reset, clear, enable, count)

    @always(HALF_CLOCK)
    def clock_generator():
        clock.next = not clock

    @instance
    def reset_generator():
        reset.next = True
        yield delay(100)
        reset.next = False
        while True:
            yield delay(1000)

    @instance
    def stimulus():
        yield delay(150)
        enable.next = True
        yield delay(1000)
        enable.next = False

        yield delay(100)
        clear.next = True
        yield delay(CLOCK)
        clear.next = False

    return inst, clock_generator, reset_generator, stimulus

def simulate(n):
    tb = traceSignals(test)
    sim = Simulation(tb)
    sim.run(n)

def convert():
    clock = Signal(bool(0))
    reset = Signal(bool(0))
    clear = Signal(bool(0))
    enable = Signal(bool(0))
    count = Signal(intbv(0)[WIDTH:0])

    toVerilog(counter, clock, reset, clear, enable, count)

if __name__ == ' __main__':
    convert()
    simulate(20000)

```

When I run this in 0.1dev, I get this and no .vcd file is generated.

```
C:/MyPython/myhdl_demo/counter.py:72: UserWarning: 
	toVerilog(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html
  toVerilog(counter, clock, reset, clear, enable, count)
C:\MyPython\myhdl_demo\venv\lib\site-packages\myhdl\conversion\_toVerilog.py:296: ToVerilogWarning: Output port is read internally: count
  category=ToVerilogWarning
C:/MyPython/myhdl_demo/counter.py:60: UserWarning: 
	traceSignals(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html
  tb = traceSignals(test)
<class 'myhdl._SuspendSimulation'>: Simulated 20000 timesteps

Process finished with exit code 0

```

It must be something simple but I haven’t found it yet.

Thanks.

---

<div class="post-metadata">

**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [March 23, 2018, 10:23am UTC](https://discourse.myhdl.org/t/moving-to-0-1dev-broke-my-design/259/2 "2018-03-23T10:23:28Z")

</div>

Nothing broke …  
I ran your code locally and it generates the Verilog code and the .vcd file:

 ![image](https://canada1.discourse-cdn.com/flex030/uploads/myhdl/original/1X/2295a8124ea6f6cc2f8e5ec73dd92bc42090eedc.png)

In MyHDL 0,1dev a new decorator `@block` has been introduced and the warnings printed out have to do with the fact that you haven’t used it. Unfortunately they are sent to _stderr_ and hence turn up **red**.

It is the idea that in the next release this `@block` decorator usage will become mandatory as it opens up possibilities to enhance the V\* code generation among others.

Maybe someone (@cfelton, @devbisme, …) can find the time to make a short but all-inclusive example?

Regards,  
Josy