# Newbie questions: trying to understand Verilog conversion behavior

**URL:** <https://discourse.myhdl.org/t/newbie-questions-trying-to-understand-verilog-conversion-behavior/117>\
**Category:** Bug\
**Created:** [September 14, 2016, 9:52pm UTC](https://discourse.myhdl.org/t/newbie-questions-trying-to-understand-verilog-conversion-behavior/117 "2016-09-14T21:52:33Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![haunma](https://avatars.discourse-cdn.com/v4/letter/h/a4c791/32.png) [@haunma](https://discourse.myhdl.org/u/haunma)\
**Post date:** [September 14, 2016, 9:52pm UTC](https://discourse.myhdl.org/t/newbie-questions-trying-to-understand-verilog-conversion-behavior/117/1 "2016-09-14T21:52:33Z")

</div>

Hi everyone,

I just posted this to the mailman list, then realized I should have come here instead. Should this Discourse link be added to the [myhdl.org](http://myhdl.org) Support-\>Community page?

I’m new to MyHDL, using it with a Digilent “Arty” board and Vivado to learn FPGAs and HDL in general. So far, I’ve found the documentation to be excellent and I haven’t had any problems with simple LED flashing, PWM, etc. Along the way I’ve accumulated some questions however:

1. I would like to parameterize certain hardware modules like I see in the examples, e.g. I have the following “Timepulse” module:

Here “interval” is intended to be taken as a constant, for the purposes of simulation and conversion. However, the Python code

```
if count == interval - 1:
    count.next = 0
else:
    count.next = count + 1

if count == interval - 1:
    q.next = 1
elif count == 0:
    q.next = 0

```

is converted to the following Verilog:

```
if (($signed({1'b0, count}) == (100000000 - 1))) begin
    count <= 0;
end
else begin
    count <= (count + 1);
end
case (count)
    (-'h1): begin
        q <= 1;
    end
    'h0: begin
        q <= 0;
    end
endcase

```

I don’t understand where all the signed-arithmetic handling comes from. Intuitively, I thought the Verilog should be the same whether my expression uses “interval-1” or “interval”, because both are large positive constants within the range of the count intbv. But in fact when I take away the -1, the signed-number handling goes away too. What am I doing wrong?

1. When converting to Verilog, do the input/output port names always follow the names in the definition of the top-level Python function? E.g. in the StopWatch tutorial, we have

`def StopWatch(tens_led, ones_led, tenths_led, startstop, reset, clock):`

so upon conversion, the Verilog code uses the names “tens\_led”, “ones\_led”, etc. as the inputs and outputs. But when targeting a dev board, I would like to assign those ports to existing port names defined in my constraints file.

It seems like there should be a way to give these names when I instantiate StopWatch, instead of having to make the names match between my Python code (at a high and logical level) and my constraints file (at a low and hardware level). Am I missing some alternative?

Thanks,

Mark

---

<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [September 16, 2016, 1:52am UTC](https://discourse.myhdl.org/t/newbie-questions-trying-to-understand-verilog-conversion-behavior/117/2 "2016-09-16T01:52:03Z")

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@haunma yes a link should be added - hmmm, I swear someone did at some point.

---

<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [September 16, 2016, 2:01am UTC](https://discourse.myhdl.org/t/newbie-questions-trying-to-understand-verilog-conversion-behavior/117/3 "2016-09-16T02:01:04Z")

</div>

@haunma as I mentioned in the mailing-list (I will re-post it here incase others run across a similar issue), this looks like a bug and we need to create a test case and then fix it. In the near-term you can work around it with:

```python
    count = Signal(intbv(0, min=0, max=interval))
    maxcnt = interval-1
    @always_seq(clock.posedge, reset=reset)
    def beh():
        if count == maxcnt:
            count.next = 0
        else:
            count.next = count + 1

        if count == maxcnt:
            q.next = 1
        elif count == 0:
            q.next = 0

    return beh

```

which generates:

```auto
always @(posedge clock, negedge reset) begin: TIMEPULSE_BEH
    if (reset == 0) begin
        count <= 0000000;
        q <= 0;
    end
    else begin
        if ((count == 99999999)) begin
            count <= 0;
        end
        else begin
            count <= (count + 1);
        end
        case (count)
            'h5f5e0ff: begin
                q <= 1;
            end
            'h0: begin
                q <= 0;
            end
        endcase
    end
end

```

The documentation should be double checked to make sure this is not a known limitation.

Regards,  
Chris