# Problem while converting to VHDL code

**URL:** <https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89>\
**Category:** Support\
**Created:** [June 16, 2016, 4:40pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89 "2016-06-16T16:40:04Z")\
**Posts on this page:** 15\
**Page:** 1

<div class="post-metadata">

**Author:** ![Ravi\_Jain](https://avatars.discourse-cdn.com/v4/letter/r/47e85d/32.png) [@Ravi\_Jain](https://discourse.myhdl.org/u/Ravi_Jain)\
**Post date:** [June 16, 2016, 4:40pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/1 "2016-06-16T16:40:04Z")

</div>

1. While verifying converted output into verilog and vhdl sequentially as in below, it causes problems.

Error:

` `

```

E AttributeError: ‘NoneType’ object has no attribute ‘f_globals’
```

File “C:\Users\Ravi\virtualenvs\myhdl\_WinCosim\lib\site-packages\myhdl-1.0.dev0-py3.5.egg\myhdl\conversion\_analyze.py”, line 174  
AttributeError

2 .

MyHDL Snippet.

```
mdiodata.rddata.next = mdiodata.rddata | (mdio_interface.inn << mdiodata.rdindex)

```

Converted to:

```
management_6_mdiodata_rddata <= (management_6_mdiodata_rddata or to_unsigned(shift_left(management_6_mdio_interface_inn, to_integer(management_6_mdiodata_rdindex)), 16));

```

Error:

```
test.vhd:259:112: no overloaded function found matching 'shift_left'

test.vhd:259:101: no overloaded function found matching 'to_unsigned'

```

By spltting the above assignment use to to\_unsigned can be avoided but problem persists with shift\_left.

---

<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [June 16, 2016, 5:11pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/2 "2016-06-16T17:11:47Z")

</div>

@Ravi_Jain when posting issues / problems you should **sandbox** the problem, make sure you can repeat it with a simple example. After you have done the sandbox experiment, then post the code for the simple example. This helps: 1) it shows you have done due diligence trying to resolve the issue; 2) others can easily exercise the code snip in question and provide feedback.

Regards,  
Chris

---

<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [June 16, 2016, 5:13pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/3 "2016-06-16T17:13:27Z")

</div>

@Ravi_Jain also, since you are not doing cosimulation you should use the master branch and not the @josyb branch (for now). It will be easier to debug if there is a problem.

---

<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [June 16, 2016, 5:20pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/4 "2016-06-16T17:20:00Z")

</div>

@Ravi_Jain you need to deal with the first error, switch back to the myhdl master branch.

---

<div class="post-metadata">

**Author:** ![Ravi\_Jain](https://avatars.discourse-cdn.com/v4/letter/r/47e85d/32.png) [@Ravi\_Jain](https://discourse.myhdl.org/u/Ravi_Jain)\
**Post date:** [June 16, 2016, 6:42pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/5 "2016-06-16T18:42:06Z")

</div>

I shall keep that(@sandboxing a problem) in mind from the next time I post.  
The simple example : [https://gist.github.com/ravijain056/8e9bff5d7a16b95cb24a7d777711bbb1](https://gist.github.com/ravijain056/8e9bff5d7a16b95cb24a7d777711bbb1)

I am using the master branch from the beginning.

The first error persists in the example.  
I found the a workaround for second error while trying to sandbox the problem. The problem being usage of boolean as a signal.(As per my understanding).  
Getting new error after solving the second.

```
ghdl.exe: Cannot find entity or configuration test_top.

```

Side problem faced : variable name out clashes with reserved keyword in vhdl.

Ghdl version used - 0.33 - win32 : [https://sourceforge.net/projects/ghdl-updates/files/Builds/ghdl-0.33/](https://sourceforge.net/projects/ghdl-updates/files/Builds/ghdl-0.33/)

---

<div class="post-metadata">

**Author:** ![Ravi\_Jain](https://avatars.discourse-cdn.com/v4/letter/r/47e85d/32.png) [@Ravi\_Jain](https://discourse.myhdl.org/u/Ravi_Jain)\
**Post date:** [June 16, 2016, 7:14pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/6 "2016-06-16T19:14:26Z")

</div>

@josyb  
Hey could you check up on the ghdl setup for windows i am using. Not so confident.

Ghdl version used - 0.33 - win32 : [https://sourceforge.net/projects/ghdl-updates/files/Builds/ghdl-0.33/](https://sourceforge.net/projects/ghdl-updates/files/Builds/ghdl-0.33/)

---

<div class="post-metadata">

**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [June 16, 2016, 7:28pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/7 "2016-06-16T19:28:30Z")

</div>

I too have a problem with GHDL, so I use the Altera Starter Edition version of ModelSIm 😀

---

<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [June 16, 2016, 7:59pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/8 "2016-06-16T19:59:08Z")

</div>

@Ravi_Jain with your sandbox version I get no errors, tested with `vcom` and `iverilog`, I don’t have the latest version of GHDL installed.

---

<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [June 16, 2016, 7:59pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/9 "2016-06-16T19:59:28Z")

</div>

@Ravi_Jain feel free to only test verilog and move on at this point.

---

<div class="post-metadata">

**Author:** ![Ravi\_Jain](https://avatars.discourse-cdn.com/v4/letter/r/47e85d/32.png) [@Ravi\_Jain](https://discourse.myhdl.org/u/Ravi_Jain)\
**Post date:** [June 16, 2016, 8:01pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/10 "2016-06-16T20:01:50Z")

</div>

Did you uncomment verify\_convert() lines at the bottom? To test the first error.

---

<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [June 16, 2016, 8:04pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/11 "2016-06-16T20:04:36Z")

</div>

Yes, I indicated I tested modelsim VHDL and Icarus verilog:

```python
verify.simulator = 'iverilog'
assert testInst.verify_convert() == 0

```

```python
verify.simulator = 'vcom'
assert testInst.verify_convert() == 0

```

I tested in two separate runs, not executed back to back.

---

<div class="post-metadata">

**Author:** ![Ravi\_Jain](https://avatars.discourse-cdn.com/v4/letter/r/47e85d/32.png) [@Ravi\_Jain](https://discourse.myhdl.org/u/Ravi_Jain)\
**Post date:** [June 16, 2016, 8:06pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/12 "2016-06-16T20:06:41Z")

</div>

The problem is that the error comes up when you try to do it in one run.

---

<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [June 16, 2016, 8:07pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/13 "2016-06-16T20:07:24Z")

</div>

Don’t do that then.

(it says I need 20 chars)  
(…)

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<div class="post-metadata">

**Author:** ![Ravi\_Jain](https://avatars.discourse-cdn.com/v4/letter/r/47e85d/32.png) [@Ravi\_Jain](https://discourse.myhdl.org/u/Ravi_Jain)\
**Post date:** [June 16, 2016, 8:09pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/14 "2016-06-16T20:09:04Z")

</div>

Okay, I will just use verilog and move on then.

---

<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [June 16, 2016, 8:09pm UTC](https://discourse.myhdl.org/t/problem-while-converting-to-vhdl-code/89/15 "2016-06-16T20:09:36Z")

</div>

Re-instantiate it before testing the conversion again.

```python
testInst = test_top()
verify.simulator = 'iverilog'
assert testInst.verify_convert() == 0

testInst = test_top()
verify.simulator = 'vcom'
assert testInst.verify_convert() == 0

```