# Python comments into generated verilog as comments

**URL:** <https://discourse.myhdl.org/t/python-comments-into-generated-verilog-as-comments/221>\
**Category:** Support\
**Created:** [September 7, 2017, 4:11pm UTC](https://discourse.myhdl.org/t/python-comments-into-generated-verilog-as-comments/221 "2017-09-07T16:11:44Z")\
**Posts on this page:** 10\
**Page:** 1

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**Author:** ![kranerup](https://avatars.discourse-cdn.com/v4/letter/k/258eb7/32.png) [@kranerup](https://discourse.myhdl.org/u/kranerup)\
**Post date:** [September 7, 2017, 4:11pm UTC](https://discourse.myhdl.org/t/python-comments-into-generated-verilog-as-comments/221/1 "2017-09-07T16:11:45Z")

</div>

Is there a way to get comments from MyHDL code output as comments in the generated Verilog code?  
We need a way to add lint waivers as comments in the Verilog code and since the Verilog is generated from MyHDL the comments needs to come from the MyHDL source.

If there is no way to do this currently, I would be grateful for any hints on how we could add this to MyHDL.

Kenny

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**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [September 8, 2017, 11:56am UTC](https://discourse.myhdl.org/t/python-comments-into-generated-verilog-as-comments/221/2 "2017-09-08T11:56:29Z")

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Hi Kenny,

The conversion to V\* relies on Python’s AST module which discards comments.  
What do these _lint waivers_ look like (both in the MyHDL and the Verilog code)?

Regards,

Josy

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<div class="post-metadata">

**Author:** ![kranerup](https://avatars.discourse-cdn.com/v4/letter/k/258eb7/32.png) [@kranerup](https://discourse.myhdl.org/u/kranerup)\
**Post date:** [September 8, 2017, 1:04pm UTC](https://discourse.myhdl.org/t/python-comments-into-generated-verilog-as-comments/221/3 "2017-09-08T13:04:05Z")

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The lint waivers in the Verilog code should be done by appending “//  
cn\_lint\_off\_line CN\_” to each waived line.  
How this should be done in MyHDL is not obvious. One simple idea would be  
to take end-of-line comments from the Python code and turn them into  
corresponding comment in the Verilog.

MyHDL:  
a.next = b + c # cn\_lint\_off\_line CN\_  
translated to Verilog:  
a \<= b + c // cn\_lint\_off\_line CN\_

But if the comments are discarded/unavailable in AST then that may not be  
possible. Is the source file and line number available in the AST? Then  
maybe it’s possible to get the comment from the original source when doing  
the verilog conversion.

```
 Kenny
```

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<div class="post-metadata">

**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [September 8, 2017, 2:43pm UTC](https://discourse.myhdl.org/t/python-comments-into-generated-verilog-as-comments/221/4 "2017-09-08T14:43:32Z")

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Kenny,

I don’t do Verilog, but I wonder why you would need the lint waiver(s)? Or perhaps the example you gave is too simple?

IMHO MyHDL should generate lint-free code…?

There is Baron and RedBaron, which generate a Full Syntax Tree, this is with all source text included, but its deployment in MyHDL will take a while. Not sure if anybody is working/studying this, perhaps @hgomersall?

Regards,

Josy

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<div class="post-metadata">

**Author:** ![hgomersall](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/hgomersall/32/10_2.png) [@hgomersall](https://discourse.myhdl.org/u/hgomersall)\
**Post date:** [September 8, 2017, 3:29pm UTC](https://discourse.myhdl.org/t/python-comments-into-generated-verilog-as-comments/221/5 "2017-09-08T15:29:23Z")

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It’s one of those “When I have some time” projects. I think there is huge scope for using an FST but it obviously needs some work!

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<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [September 8, 2017, 10:38pm UTC](https://discourse.myhdl.org/t/python-comments-into-generated-verilog-as-comments/221/6 "2017-09-08T22:38:43Z")

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You can get comments in the converted code by using doc strings. Personally I don’t think it would be worth it to convert the comments in the myhdl.generators to the converted code since the doc strings exist (just my opinion).

```python
import myhdl
from myhdl import Signal, ResetSignal, intbv, always_seq, always_comb

@myhdl.block
def my_awesome_amazing_block_of_logic(clock, reset, x, y):
    """
    This block of logic is so fantastic it will blow you mind,
    you have never seen anything like it. It is absolutely 
    amazing ....
    """
    b = Signal(y.val)
    
    @always_seq(clock.posedge, reset=reset)
    def beh_atch():
        """More amazing sequential logic"""
        y.next = b - 1
        
    @always_comb
    def beh_itching():
        """Look at how it is combinatorial"""
        b.next = x + 1
        
    return myhdl.instances()

clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=False)
x = Signal(intbv(0, min=-16, max=16))
y = Signal(intbv(0, min=-17, max=17))
inst = my_awesome_amazing_block_of_logic(clock, reset, x, y)
inst.convert()
%less my_awesome_amazing_block_of_logic.v

```

```auto
// File: my_awesome_amazing_block_of_logic.v
// Generated by MyHDL 1.0dev
// Date: Fri Sep 8 17:35:42 2017

`timescale 1ns/10ps

module my_awesome_amazing_block_of_logic (
    clock,
    reset,
    x,
    y
);
// This block of logic is so fantastic it will blow you mind,
// you have never seen anything like it. It is absolutely 
// amazing ....

input clock;
input reset;
input signed [4:0] x;
output signed [5:0] y;
reg signed [5:0] y;

wire signed [5:0] b;

// Look at how it is combinatorial

assign b = (x + 1);

// More amazing sequential logic
always @(posedge clock) begin: MY_AWESOME_AMAZING_BLOCK_OF_LOGIC_BEH_ATCH
    if (reset == 0) begin
        y <= 0;
    end
    else begin
        y <= (b - 1);
    end
end

endmodule

```

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<div class="post-metadata">

**Author:** ![kranerup](https://avatars.discourse-cdn.com/v4/letter/k/258eb7/32.png) [@kranerup](https://discourse.myhdl.org/u/kranerup)\
**Post date:** [September 9, 2017, 8:39am UTC](https://discourse.myhdl.org/t/python-comments-into-generated-verilog-as-comments/221/7 "2017-09-09T08:39:15Z")

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Thanks, doc strings was a good idea. That could be a way forward. The only  
problem with doc strings is that they are not put on the same line as the  
code, as per my example. But I think I can create a script that  
post-processes the comments and moves them to the end of the correct line.  
Since the layout of the generated Verilog is very regular I think it might  
work.

```
Kenny
```

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<div class="post-metadata">

**Author:** ![cfelton](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/cfelton/32/3_2.png) [@cfelton](https://discourse.myhdl.org/u/cfelton)\
**Post date:** [September 9, 2017, 12:52pm UTC](https://discourse.myhdl.org/t/python-comments-into-generated-verilog-as-comments/221/8 "2017-09-09T12:52:13Z")

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@kranerup correct it doesn’t help with your example, I hadn’t read the complete thread just the OP. I agree with @josyb you shouldn’t need to disable the linter, is there a specific example (lint error/warning) you are trying to avoid? Is the linter too strict? Which lint tool are you using?

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<div class="post-metadata">

**Author:** ![kranerup](https://avatars.discourse-cdn.com/v4/letter/k/258eb7/32.png) [@kranerup](https://discourse.myhdl.org/u/kranerup)\
**Post date:** [September 11, 2017, 11:44am UTC](https://discourse.myhdl.org/t/python-comments-into-generated-verilog-as-comments/221/9 "2017-09-11T11:44:19Z")

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We can’t avoid triggering the lint rules. We deliver the verilog to customers that then run with their own set of rules. As often is the case with linters the rules are triggered and we analyze the code only to find that there is not a real problem. Thus we need to waive it or rewrite the code just for the sake of the linter.

We will go with the solution to use doc strings that are then post processed to become end of line comments. It would’ve been nice to be able to waive it on the same line in MyHDL but it seems not possible.

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<div class="post-metadata">

**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [September 11, 2017, 12:38pm UTC](https://discourse.myhdl.org/t/python-comments-into-generated-verilog-as-comments/221/10 "2017-09-11T12:38:20Z")

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Can you show us a (large enough) piece of actual MyHDL code to give us a feeling where you want to waive the linters?  
Is there a possibility to waive the complete file?