# REG intialization without 'always\_seq' (solved)

**URL:** <https://discourse.myhdl.org/t/reg-intialization-without-always-seq-solved/229>\
**Category:** Support\
**Created:** [October 9, 2017, 7:17pm UTC](https://discourse.myhdl.org/t/reg-intialization-without-always-seq-solved/229 "2017-10-09T19:17:23Z")\
**Posts on this page:** 5\
**Page:** 1

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**Author:** ![pythondsp](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/pythondsp/32/74_2.png) [@pythondsp](https://discourse.myhdl.org/u/pythondsp)\
**Post date:** [October 9, 2017, 7:17pm UTC](https://discourse.myhdl.org/t/reg-intialization-without-always-seq-solved/229/1 "2017-10-09T19:17:23Z")

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[http://fpga-designs-with-myhdl.readthedocs.io/en/latest/myhdl/fsm.html#square-wave-ex-py](http://fpga-designs-with-myhdl.readthedocs.io/en/latest/myhdl/fsm.html#square-wave-ex-py)

- In the above link, the signal ‘t’ (at Line 20) is initialized using ‘always\_seq’ decorator; which uses the ‘reset’ signal to set the initial value.

- Is is possible to generate the Verilog/VHDL code as "reg [3:0] t = 0 ", instead of using reset signal to set the initial value.

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [October 10, 2017, 12:05pm UTC](https://discourse.myhdl.org/t/reg-intialization-without-always-seq-solved/229/2 "2017-10-10T12:05:38Z")

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Initial value is always supported in simulation.  
It is also supported in conversion when using the last version on github.

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<div class="post-metadata">

**Author:** ![pythondsp](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/pythondsp/32/74_2.png) [@pythondsp](https://discourse.myhdl.org/u/pythondsp)\
**Post date:** [October 10, 2017, 7:47pm UTC](https://discourse.myhdl.org/t/reg-intialization-without-always-seq-solved/229/3 "2017-10-10T19:47:23Z")

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> [@DrPi](#):
>
> It is also supported in conversion when using the last version on github.

It is not working.  
I installed MyHDL using conda and pip. Did I do something wrong with installation.  
Python Version : 3.6.2, MyHDL 0.9.0.

I tried with MyHDL 1.0 as well, but after conversion, the reg is defined as “reg [3:0] t” (not as reg [3:0] t = 0).

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<div class="post-metadata">

**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [October 11, 2017, 11:53am UTC](https://discourse.myhdl.org/t/reg-intialization-without-always-seq-solved/229/4 "2017-10-11T11:53:29Z")

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Have you used set _initial\_values_ parameter to True when converting ?  
Something like :  
dut\_inst.convert(hdl=‘VHDL’, name=“RandomGenerator”, path="./vhdl", initial\_values=True)

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<div class="post-metadata">

**Author:** ![pythondsp](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/pythondsp/32/74_2.png) [@pythondsp](https://discourse.myhdl.org/u/pythondsp)\
**Post date:** [October 11, 2017, 6:36pm UTC](https://discourse.myhdl.org/t/reg-intialization-without-always-seq-solved/229/5 "2017-10-11T18:36:52Z")

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Thank you.

It worked with MyHDL 1.0.  
Previously, I was using .covert function with MyHDL 0.9.0, that is why I was getting error.