# Saving testbench data to file (solved)

**URL:** <https://discourse.myhdl.org/t/saving-testbench-data-to-file-solved/234>\
**Category:** Support\
**Created:** [October 14, 2017, 7:09pm UTC](https://discourse.myhdl.org/t/saving-testbench-data-to-file-solved/234 "2017-10-14T19:09:10Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![pythondsp](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/pythondsp/32/74_2.png) [@pythondsp](https://discourse.myhdl.org/u/pythondsp)\
**Post date:** [October 14, 2017, 7:09pm UTC](https://discourse.myhdl.org/t/saving-testbench-data-to-file-solved/234/1 "2017-10-14T19:09:10Z")

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1. In the below link, I tried to saved the simulation-data in the file. Do you have any suggestion for this, or is it fine? This looks fine to me, but need advice as I am new to MyHDL (only 10 days experience).

2. I am trying to convert my VHDL/Verilog templates into MyHDL-templates. Currently, I am following MyHDL official doc only. Do you have some more suggestions for other resources?

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [October 16, 2017, 6:28am UTC](https://discourse.myhdl.org/t/saving-testbench-data-to-file-solved/234/2 "2017-10-16T06:28:58Z")

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This might be of some help : [MyHDL cheat sheet](http://discourse.myhdl.org/t/myhdl-cheat-sheet/130)  
I started a tips and tricks but it is far from publishable.

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<div class="post-metadata">

**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [October 16, 2017, 6:42am UTC](https://discourse.myhdl.org/t/saving-testbench-data-to-file-solved/234/3 "2017-10-16T06:42:39Z")

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Just had a very quick look at your code.  
Instead of modifying clk to an int, you can print with (“0”, “1”)[clk].  
Another possibility is to create a Bool class inheriting bool and overcharging str method.