# Signed error with lshift

**URL:** <https://discourse.myhdl.org/t/signed-error-with-lshift/539>\
**Category:** Support\
**Created:** [April 24, 2022, 4:41am UTC](https://discourse.myhdl.org/t/signed-error-with-lshift/539 "2022-04-24T04:41:56Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![steveg](https://avatars.discourse-cdn.com/v4/letter/s/ecae2f/32.png) [@steveg](https://discourse.myhdl.org/u/steveg)\
**Post date:** [April 24, 2022, 4:41am UTC](https://discourse.myhdl.org/t/signed-error-with-lshift/539/1 "2022-04-24T04:41:56Z")

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Hi All,

I want to shift a signal left if the msbit is false in a clocked process… (Verilog has no issue with this)

shift.next = mult \<\< ~mult[WIDTH2M-1]

i.e. of mult[WIDTH2M-1] is false, shift left otherwise do not.

This gives an error  
File “D:\Lumetrica\_Projects\myHDL\_IP\math\floating\_point\fp\_multiply.py”, line 41, in comb2\_logic  
shift.next = mult \<\< int(~mult[WIDTH2M-1])  
File “d:\lumetrica\_projects\adc\_interface\src\myhdl\myhdl\_Signal.py”, line 434, in **lshift**  
return self.\_val \<\< other  
File “d:\lumetrica\_projects\adc\_interface\src\myhdl\myhdl\_intbv.py”, line 257, in **lshift**  
return intbv(int(self.\_val) \<\< other)  
ValueError: negative shift count

My Signals are modbv() and not intbv - if that matters

If there is a way to cast this to avoid the error I haven’t found it yet.

Turning it into an ‘if … else’ is really quite messy.- but I guess I can do this.

Do I register this as a bug or is it correct behaviour?

Regards,

Steve.

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**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [April 24, 2022, 10:44am UTC](https://discourse.myhdl.org/t/signed-error-with-lshift/539/2 "2022-04-24T10:44:02Z")

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Hi Steve,

This is in simulation, I assume.  
`~a[x]` resolves to either _-1_ or _-2_ which is a negative shift and raises a ValueError in Python.  
Correct behavior.  
` c.next = b << (not b[3])` will simulate correctly and convert to:  
`assign c = (b << (!b[3]));`  
and  
`c <= shift_left(b, to_integer((not bool(b(3)))));`  
The VHDL is correct. I assume that Verilog will have no issue either.

Regards,  
Josy

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**Author:** ![steveg](https://avatars.discourse-cdn.com/v4/letter/s/ecae2f/32.png) [@steveg](https://discourse.myhdl.org/u/steveg)\
**Post date:** [April 24, 2022, 8:37pm UTC](https://discourse.myhdl.org/t/signed-error-with-lshift/539/3 "2022-04-24T20:37:34Z")

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Hi Josy,

This was in verilog generation and not simulation.

You gave me the clue though the shift distance has to be cast as an int so …  
mult.next = mult \<\< int(~mult[WIDTH2M-1]) gave the correct result

assign shift = (mult \<\< (~mult[(16 - 1)]));

Thank you (again)

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<div class="post-metadata">

**Author:** ![steveg](https://avatars.discourse-cdn.com/v4/letter/s/ecae2f/32.png) [@steveg](https://discourse.myhdl.org/u/steveg)\
**Post date:** [April 24, 2022, 8:50pm UTC](https://discourse.myhdl.org/t/signed-error-with-lshift/539/4 "2022-04-24T20:50:44Z")

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Hi Josy, …

It was in simulation also (now that I checked again) and so now the mult \<\< int(not mult[… ) is the correct answer.

Steve.