# Sort signal declarations in generated VHDL

**URL:** <https://discourse.myhdl.org/t/sort-signal-declarations-in-generated-vhdl/224>\
**Category:** Enhancement Request\
**Created:** [October 5, 2017, 8:16am UTC](https://discourse.myhdl.org/t/sort-signal-declarations-in-generated-vhdl/224 "2017-10-05T08:16:26Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [October 5, 2017, 8:16am UTC](https://discourse.myhdl.org/t/sort-signal-declarations-in-generated-vhdl/224/1 "2017-10-05T08:16:26Z")

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Hi,

Currently, each time a python source file is converted to VHDL, signal declarations are in a different order.  
I propose to sort signal declarations in generated VHDL to always get the same order.  
The reason why is to be able to easily compare 2 generated files.  
This is useful in various situations :

- Upgrading MyHDL : check that the output code is still the same.
- Comparing algorithms : compare generated files
- Working on a source file : compare generated file with previous version
- Other situations where 2 generated files have to be compared

The correction is very simple. Just add the two following lines at the beginning of \_writeSigDecls() function in \_toVHDL module :

```python
    siglist.sort(key=lambda x:x._name.lower())
    memlist.sort(key=lambda x:x.name.lower())

```

I guess the same could be done in \_toVerilog module but I don’t use Verilog.

What do you think of this ?

Nicolas

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<div class="post-metadata">

**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [October 5, 2017, 9:50am UTC](https://discourse.myhdl.org/t/sort-signal-declarations-in-generated-vhdl/224/2 "2017-10-05T09:50:36Z")

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I just realised there is the same problem with process sensitivity list.

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**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [October 5, 2017, 12:56pm UTC](https://discourse.myhdl.org/t/sort-signal-declarations-in-generated-vhdl/224/3 "2017-10-05T12:56:59Z")

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Nicolas,

I have done about that in my local MyHDL source, I keep the names as they are (no .lower()) but I tabulate them for easier reading.

I replaced the sensitivity list by the VHDL _all_ keyword

Regards,

Josy

P.S. I stopped submitting PRs a long time ago, because of lack of interest from our BDFL. One can only wait for so long …

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<div class="post-metadata">

**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [October 5, 2017, 2:10pm UTC](https://discourse.myhdl.org/t/sort-signal-declarations-in-generated-vhdl/224/4 "2017-10-05T14:10:15Z")

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Josy,

> [@josyb](#):
>
> P.S. I stopped submitting PRs a long time ago, because of lack of interest from our BDFL. One can only wait for so long …

Alas, this is so true…  
Merging PRs will be a nightmare.