# Synthesizing RAM in Quartus Prime

**URL:** <https://discourse.myhdl.org/t/synthesizing-ram-in-quartus-prime/450>\
**Category:** Uncategorized\
**Created:** [February 9, 2021, 4:24pm UTC](https://discourse.myhdl.org/t/synthesizing-ram-in-quartus-prime/450 "2021-02-09T16:24:58Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![kc64](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/kc64/32/83_2.png) [@kc64](https://discourse.myhdl.org/u/kc64)\
**Post date:** [February 9, 2021, 4:24pm UTC](https://discourse.myhdl.org/t/synthesizing-ram-in-quartus-prime/450/1 "2021-02-09T16:24:58Z")

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According to the Quartus documentation on [targetting embedded RAM](https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_ram.htm), you must specify the directives in the Verilog code as comments. Is this the prescribed method when using this platform or is there another? Is there a way to propagate such a comment into the Verilog or must I edit the .v file after each compile?

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**Author:** ![josyb](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/josyb/32/5_2.png) [@josyb](https://discourse.myhdl.org/u/josyb)\
**Post date:** [February 9, 2021, 7:01pm UTC](https://discourse.myhdl.org/t/synthesizing-ram-in-quartus-prime/450/2 "2021-02-09T19:01:35Z")

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Hi Kevin,

Unfortunately you will have to edit the .v file after every generation. To infer RAM storage we use the built-in type `list ` which , even if we wanted to, can not not be augmented with _attributes_.

Regards,  
Josy

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<div class="post-metadata">

**Author:** ![kc64](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/kc64/32/83_2.png) [@kc64](https://discourse.myhdl.org/u/kc64)\
**Post date:** [February 9, 2021, 8:47pm UTC](https://discourse.myhdl.org/t/synthesizing-ram-in-quartus-prime/450/3 "2021-02-09T20:47:33Z")

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Thank you, Josy. I opted for a work-around. It’s not perfect and it’s not parameterized, but it works.

```
    ...
    inst.convert(hdl=hdl)

if __name__ == ' __main__':
    simulate(test_inst)
    convert()

    if not USE_QUARTUS:
        exit()

    import re

    # build the verilog filename just generated
    file = __file__.split('.')
    file[-1] = 'v'
    file = '.'.join(file)

    # update the file to patch the Quartus directive for using memory blocks    
    with open(file, 'r') as v:
        data = v.read()
    new_data = re.sub('(reg.*m9kb.*;)', r'(* ramstyle = "M9K" *) \1', data, flags=re.M)

    with open(file, 'w') as v:
        v.write(new_data)
```