# 'tuple' object has no attribute 'config\_sim'

**URL:** https://discourse.myhdl.org/t/tuple-object-has-no-attribute-config-sim/361
**Category:** Support
**Created:** [February 24, 2019, 1:53pm UTC](https://discourse.myhdl.org/t/tuple-object-has-no-attribute-config-sim/361 "2019-02-24T13:53:02Z")
**Posts on this page:** 2
**Page:** 1

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### Author: ![wisdomz](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/wisdomz/32/113_2.png) [@wisdomz](https://discourse.myhdl.org/u/wisdomz)
#### Post date: [February 24, 2019, 1:53pm UTC](https://discourse.myhdl.org/t/tuple-object-has-no-attribute-config-sim/361/1 "2019-02-24T13:53:02Z")

</div>

I get the following fir example design from open source

from myhdl import \*

#=[10,11,13,154]

def m\_firfilt(clock, reset, sig\_in, sig\_out, coef):  
“”"  
“”"  
taps = [Signal(intbv(0, min=sig\_in.min, max=sig\_in.max)) for ii in range(len(coef))]  
#coef\_data = [Signal(intbv(0, min=sig\_in.min, max=sig\_in.max)) for ii in coef]

```
# @todo: check the coefficients, needs to be the correct type
# could even detect float here, scale and convert to int
coef = tuple(coef)  
mshift = len(sig_in)-1
print(mshift)
print(taps)

@always(clock.posedge)
def rtl_sop():
    if reset:
        for ii in range(len(coef)):
            taps[ii].next = 0
        sig_out.next = 0
    else:
        sop = 0
        # Note this adds an extra delay! (Group delay N/2+1)
        for ii in range(len(coef)):
            if ii == 0:
                taps[ii].next = sig_in 
            else: 
                taps[ii].next = taps[ii-1]
            c = coef[ii]
            sop = sop + (taps[ii] * c)
        sig_out.next = (sop >> mshift)    

return rtl_sop

```

#Convert to Verilog

def convert():  
clk = Signal(bool(False))  
reset = ResetSignal(bool(False), bool(True), async=True)  
sig\_in= Signal(intbv(1)[8:])  
sig\_out=Signal(intbv(1)[8:])  
coef = (12,15,17,18,19,20,-3,-5,23,567,45,234)

toVerilog.timescale = “100ms/1ms”  
toVerilog(m\_firfilt, clk, reset, sig\_in,sig\_out,coef)

# convert()

and I learn the other demo , to write the test, but , it always give me some warning. Even I take more time, I have no idea how to handle it, in fact, I want to see what is the fir response. myhdl is very great tools. I try to learn it.

# -_- coding: utf-8 -_-

“”"  
Created on Sun Feb 24 16:00:51 2019  
/home/wisdom/Documents/pythoncode/myhdl/cfelton-examples/firfilt/firfilt\_testbech.py

@author: wisdom  
“”"  
import numpy as np;  
import matplotlib.pyplot as plt  
import cv2;  
import math;  
from cmath import sin  
from numpy.core.numeric import dtype  
from scipy.signal import butter, lfilter, freqz  
from scipy.fftpack import fft;

from myhdl import \*  
from firfilt import m\_firfilt

#m\_firfilt(clock, reset, sig\_in, sig\_out, coef)

# Demonstrate the use of the filter.

# First make some data to be filtered.

fs = 30.0  
T = 5 # seconds  
n = int(T \* fs) # total number of samples  
t = np.linspace(0, T, n, endpoint=False)

# “Noisy” data. We want to recover the 1.2 Hz signal from this.

data = np.sin(1.2_2_np.pi_t) + 1.5_np.cos(9_2_np.pi_t) + 0.5_np.sin(12.0_2_np.pi\*t)

def m\_firfilt\_testbench():  
sMax = 2\*\*15; sMin=-1\*sMax  
clock = Signal(bool(0))  
reset = ResetSignal(0,active = 0, async= True)  
sig\_in = Signal(intbv(0, min=sMin, max=sMax))  
sig\_out = Signal(intbv(0, min=sMin, max=sMax))  
#sig\_in = Signal(intbv(1)[8:])  
#sig\_out= Signal(intbv(1)[8:])  
coef= [12,15,17,18,19,20,-3,-5,23,567,45,234]

```
dut= m_firfilt(clock,reset,sig_in,sig_out,coef)

HALF_PERIOD = delay(10)

@always(HALF_PERIOD)
def clockGen():
    clock.next = not clock

@instance
def stimulus():
    reset.next = 1
    delay(20)
    reset.next = 0
    delay(20)
    reset.next = 1

    for i in range(1000):
        sig_in.next=i
        yield clock.negedge
    raise StopSimulation()

```

# monitor功能非常好用， 可以立即检测是否有些功能正确设计了， 类似于signalTAP

```
@instance
def monitor():
    print("sig_in sig_out")
    yield reset.posedge
    while 1:
        yield clock.posedge
        yield delay(1)
        if sig_in >200 and sig_in<300:
            print(" %s %s"%(int(sig_in),int(sig_out)))
return clockGen, stimulus,monitor,dut

```

# tb=m\_firfilt\_testbench() tb.config\_sim(trace=True) tb.run\_sim()

I run it on Ｓｐｙｄｅｒ， ａｎｄ system have the following message.

AttributeError: ‘tuple’ object has no attribute ‘config\_sim’

Thank you

Wisdom

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<div class="post-metadata">

### Author: ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)
#### Post date: [February 25, 2019, 10:08am UTC](https://discourse.myhdl.org/t/tuple-object-has-no-attribute-config-sim/361/2 "2019-02-25T10:08:14Z")

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Hi,  
Can you please rewrite your message with correct formatting to make it easily readable ?
