# Using lists of signals in myhdl

**URL:** <https://discourse.myhdl.org/t/using-lists-of-signals-in-myhdl/448>\
**Category:** Support\
**Created:** [February 4, 2021, 4:39pm UTC](https://discourse.myhdl.org/t/using-lists-of-signals-in-myhdl/448 "2021-02-04T16:39:32Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![mhdghd](https://avatars.discourse-cdn.com/v4/letter/m/b3f665/32.png) [@mhdghd](https://discourse.myhdl.org/u/mhdghd)\
**Post date:** [February 4, 2021, 4:39pm UTC](https://discourse.myhdl.org/t/using-lists-of-signals-in-myhdl/448/1 "2021-02-04T16:39:32Z")

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Hello,

I am new here, and i am trying to use list of signals as the following :

> memory = [Signal(intbv(0)[32:0]) for i in range(32)]

however i am having an issuse while converting to verilog as follows :

> ```
> 'Name' object has no attribute 'value'
> 
> ```

is here a simple way to implement that list and still be able to convert to verilog ?

best regards.

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**Author:** ![DrPi](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/drpi/32/36_2.png) [@DrPi](https://discourse.myhdl.org/u/DrPi)\
**Post date:** [February 5, 2021, 10:44am UTC](https://discourse.myhdl.org/t/using-lists-of-signals-in-myhdl/448/2 "2021-02-05T10:44:17Z")

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How/where is the list used ? In top level ports ?

A simple excerpt of code would be useful.

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**Author:** ![saudalwasly](https://yyz2.discourse-cdn.com/flex030/user_avatar/discourse.myhdl.org/saudalwasly/32/130_2.png) [@saudalwasly](https://discourse.myhdl.org/u/saudalwasly)\
**Post date:** [February 10, 2021, 8:13pm UTC](https://discourse.myhdl.org/t/using-lists-of-signals-in-myhdl/448/3 "2021-02-10T20:13:00Z")

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If you are trying to model a memory then your list of signals should be at your block scope. You also need to have a process to manage accessing your memory storage.

To get correct inference, you also need to have a set signals as ports, such as address, data, we, …

As @DrPi said, to give you more hints you need to share more code so that we understand what you are trying to do.